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STEL-2176
User Manual STel-MAN-97709
STEL-2176
Digital Mod/Demod ASIC 16/64/256 QAM Receiver with FEC QPSK/16 QAM Transmitter with FEC
R
TRADEMARKS
Stanford Telecom(R) and STEL (R) are registered trademarks of Stanford Telecommunications, Incorporated.
STEL-2176
User Manual
FOREWORD
The Telecom Component Products Division of Stanford Telecommunications, Inc., is pleased to provide its customers with this copy of the STEL 2176 User Manual. This User Manual contains product information for the STEL 2176 and is being provided to assist our customers in understanding the advantages to be gained by integrating both the receiver and transmitter functions as an integral portion of their cable modem chip. Recipients of this User Manual should note that the content contained here-in is subject to change. The content of this User Manual will be updated to reflect the latest technical data, without notice to the recipients of this document.
User Manual
STEL-2176
ERRATA for STEL-2176
Supported Modes of Operation: Downstream
FEC Annex A Annex B Annex C
16 QAM X
64 QAM X X
256 QAM
X
X
X
Upstream
STD MCNS DAVIC
BPSK
QPSK X
16 QAM X
X
X
STEL-2176
User Manual
TABLE OF CONTENTS
PARAGRAPH
KEY FEATURES..................................................................................................................................... RECEIVER........................................................................................................................................... TRANSMITTER ................................................................................................................................... INTRODUCTION .................................................................................................................................. RECEIVER OVERVIEW........................................................................................................................ TRANSMITTER OVERVIEW ................................................................................................................ MECHANICAL SPECIFICATIONS ........................................................................................................ 208-PIN SQFP PACKAGE..................................................................................................................... ELECTRICAL SPECIFICATIONS ........................................................................................................ RECEIVER ............................................................................................................................................. OVERVIEW......................................................................................................................................... FUNCTIONAL BLOCKS ...................................................................................................................... ADC.............................................................................................................................................. Microcontroller Interface................................................................................................................. Master Receive Clock Generator...................................................................................................... QAM Demodulator Blocks.............................................................................................................. FEC Decoder Blocks ....................................................................................................................... RECEIVE AND UNIVERSAL REGISTER DESCRIPTIONS .................................................................... PROGRAMMING THE 2176 RECEIVE FUNCTIONS ............................................................................. REGISTER DESCRIPTIONS.................................................................................................................. Bank 0 - Universal Registers (Group 1)............................................................................................. Bank 0 - QAM Demodulator Registers Universal Registers (Group 2) ................................................ Bank 1 - FEC Registers (Group 3)..................................................................................................... TIMING................................................................................................................................................. NO GAP, PARALLEL MODE ............................................................................................................... NO GAP, SERIAL MODE ..................................................................................................................... GAPS, PARALLEL MODE.................................................................................................................... GAPS, SERIAL MODE ......................................................................................................................... TRANSMITTER..................................................................................................................................... INTRODUCTION ................................................................................................................................ FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS ............................................................................. DATA PATH DESCRIPTION ............................................................................................................... Bit SYNC Block .............................................................................................................................. Bit Encoder Block ........................................................................................................................... Symbol Mapper Block..................................................................................................................... Nyquist FIR Filter........................................................................................................................... Interpolating Filter ......................................................................................................................... Modulator ..................................................................................................................................... 10-Bit DAC.....................................................................................................................................
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STEL-2176
TABLE OF CONTENTS
PARAGRAPH PAGE
52 52 52 53 53 54 54 54 57 65 70
CONTROL UNIT DESCRIPTION.......................................................................................................... Bus Interface Unit ........................................................................................................................... Master Transmit Clock Generator .................................................................................................... Clock Generator ............................................................................................................................. NCO.............................................................................................................................................. TRANSMIT REGISTER DESCRIPTIONS................................................................................................ Programming the 2176 Transmit and Receive Functions.................................................................... Block 2, Upstream Registers (Group 4) ............................................................................................. TIMING DIAGRAMS ............................................................................................................................ BURST TIMING EXAMPLES ................................................................................................................. RECOMMENDED INTERFACE CIRCUITS ............................................................................................
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LIST OF FIGURES
FIGURE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19. 20. 21. 22. 23. 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38. Reference A/D Wiring............................................................................................... Example Output Load Schematic................................................................................ STEL-2176 Receiver Block Diagram ............................................................................ Master Receive Clock Generator................................................................................. QAM Demodulator Blocks......................................................................................... ITU-T (J.83) Annex A FEC Subsystem ......................................................................... 16 QAM Constellation ............................................................................................... 64 QAM Constellation ............................................................................................... 256 QAM Constellation (DAVIC)................................................................................ 256 QAM Constellation (DVB/IEEE 802.14) ................................................................ Demapper................................................................................................................. De-Interleaver ........................................................................................................... ITU-T (J.83) Annex B FEC Subsystem.......................................................................... Trellis Coded Demodulator........................................................................................ 64 QAM Mapping ..................................................................................................... 256 QAM Mapping.................................................................................................... Derandomizer........................................................................................................... De-Interleaver ........................................................................................................... Downstream Output Timing (Parallel Data Output) .................................................... Downstream Output Timing (Serial Output) ............................................................... Downstream Output Timing (Parallel Data Output) .................................................... Downstream Output Timing (Parallel Data Output) .................................................... De-Interleaver External SRAM Timing........................................................................ STEL-2176 Transmitter Block Diagram........................................................................ Bit Encoder Functional Diagram................................................................................. Scrambler Block Diagram........................................................................................... DAVIC Scrambler...................................................................................................... Mapping Block Functional Diagram ........................................................................... BPSK Constellation.................................................................................................... QPSK Constellation ................................................................................................... Natural Mapping Constellation .................................................................................. Gray Coded Constellation.......................................................................................... Left Coded Constellation ........................................................................................... DAVIC Coded Constellation ...................................................................................... Right Coded Constellation ......................................................................................... Nyquist FIR Filter...................................................................................................... Interpolation Filter Block Diagram.............................................................................. Master Clock Generation ...........................................................................................
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STEL-2176
LIST OF TABLES
TABLE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
PAGE
STEL-2176 Pin Assignments ....................................................................................... Absolute Maximum Ratings ....................................................................................... Recommended Operating Conditions ......................................................................... ADC Performance Specifications ................................................................................ DC Characteristics ..................................................................................................... Read/Write Register Set............................................................................................. Write Only Registers: ................................................................................................. Group 2, Sub-Group 'A' Read/Write Registers............................................................. Sub-Group 'A' Read-Only Registers ............................................................................ SNR to ErrPwr Conversion......................................................................................... Group 2, Sub-Group 'B' Read/Write Registers ............................................................. Group 2, Sub-Group 'B' Read-Only Registers ............................................................... Group 2, Sub-Group 'C' Read/Write Registers............................................................. Group 2, Sub-Group 'C' Read-Only Registers............................................................... Group 2, Sub-Group 'D' Read/Write Registers............................................................. Group 2, Sub-Group 'D' Read-Only Registers .............................................................. Group 2, Sub-Group 'E' Read/Write Registers ............................................................. Group 2, Sub-Group 'E' Read-Only Registers ............................................................... Group 2, Sub-Group 'F' Read/Write Registers ............................................................. Group 2, Sub-Group 'F' Read-Only Registers ............................................................... Group 3, Sub-Group 'A' Read/Write Registers............................................................. Group 3, Sub-Group 'B' Read-Only Registers ............................................................... Group 3, Sub-Group 'C' Read/Write Registers............................................................. Group 3, Sub-Group 'C' Read-Only Registers............................................................... Group 3, Sub-Group 'D' Read/Write Registers............................................................. Group 3, Sub-Group 'D' Read-Only Registers .............................................................. Group 3, Sub-Group 'E' Read/Write Registers ............................................................. Group 3, Sub-Group 'E' Read-Only Registers ............................................................... Group 3, Sub-Group 'F' Read/Write Registers ............................................................. Group 3, Sub-Group 'G' Read/Write Registers............................................................. Group 3, Sub-Group 'G' Read-Only Registers .............................................................. Transmit Features...................................................................................................... Data Latching Options ............................................................................................... BIT Encoding Data Path Options................................................................................. Scrambler Parameters ................................................................................................ Sample Scramble Register Values................................................................................ Reed-Solomon Encoder Parameters............................................................................. Bit Mapping Options ................................................................................................. Differential Encoder Control....................................................................................... QPSK Differential Encoding and Phase Shift................................................................ Symbol Mapping Selections........................................................................................ Symbol Mapping ....................................................................................................... FIR Filter Configuration Options ................................................................................ 3 8 8 9 9 20 20 22 22 23 24 24 26 26 26 27 28 28 29 30 30 31 31 31 32 32 33 33 34 34 34 40 41 42 43 43 44 45 46 46 48 48 50
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LIST OF TABLES
TABLE
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 FIR Filter Coefficient Storage...................................................................................... Interpolation Filter Bypass Control ............................................................................. Interpolation Filter Signal Level Control ..................................................................... Signal Inversion Control ............................................................................................ FCW Selection........................................................................................................... Addresses of the STEL-2176 Register Groups .............................................................. Transmit Block 2 Register Data Fields ......................................................................... Clock Timing AC Characteristics................................................................................ Pulse Width AC Characteristics.................................................................................. Bit Clock Synchronization AC Characteristics.............................................................. Input Data and Clock AC Characteristics .................................................................... Write Timing AC Characteristics ................................................................................ Read Timing AC Characteristics................................................................................. NCO Loading AC Characteristics ............................................................................... Digital Output Timing AC Characteristics................................................................... TXDATAENI to TXDATAENO Timing AC Characteristics ..........................................
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STEL-2176
Introduction
KEY FEATURES
RECEIVER
n n n n n n n n n n
10-bit A/D on chip 16/64/256 QAM demodulation Selectable ITU-T (J.83), Annex A/Annex B forward error correction (FEC) MCNS, IEEE 802.14 (preliminary), DAVIC/DVB compliant Parallel or serial output data with or without gaps Viterbi decoder for Annex B Selectable Reed-Solomon decoder for Annex A and Annex B Programmable De-Interleaver Programmable De-Randomizer MPEG-2 Framing
n n n n n n n n n
Programmable control registers for maximum flexibility FIFO for optional removal of inter-frame gaps Automatic frequency control ( 200 kHz) Highly integrated receiver functions Up to 50 MHz IF input Uses inexpensive Crystal in the 25 MHz range Adaptive Channel Equalizer (ACE) to compensate for channel distortion Selectable Nyquist filter Fast acquisition
TRANSMITTER
n n n n n n n
Patented (U.S. Patent #5,412,352) Complete BPSK/QPSK/16QAM modulator Complete upstream modulator solution--serial data in, RF signal out Programmable over a wide range of data rates Numerically Controlled Oscillator (NCO) modulator provides fine frequency resolution Carrier frequencies programmable from 5 to 65 MHz Uses inexpensive crystal in 25 MHz range Operates in continuous and burst modes
n n n n n
Differential Encoder, Programmable Scrambler, and Programmable ReedSolomon FEC Encoder Programmable 64-tap FIR filter for signal shaping before modulation 10-bit DAC on chip Compatible with DAVIC, IEEE 802.14 (preliminary), Intelsat IESS-308, MCNS Standards Supports low data rates for voice applications and high data rates for wideband applications
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INTRODUCTION
The STEL-2176 is a complete subscriber-side cable modem chip that integrates both receiver and transmitter functions. It is offered in CMOS .35 micron geometry operating at 3.3 Volts with integrated DAC and ADC. Its programmable register set offers a flexible solution to meet current and evolving standards. Interleaver puts the data bits back into the original order, while Trellis and Reed-Solomon decoders handle error correction. For Annex A, a Reed-Solomon decoder decodes and corrects every 204 bytes in 188 bytes. For Annex B, there is a Viterbi decoder and a 128, 122 (code word length, information) 7-bit Reed-Solomon decoder. A derandomizer is used to unscramble the data stream. Format of the receiver output is MPEG-2 frames.
RECEIVER OVERVIEW
A 10-bit A/D converts the analog input signal. The analog input signal may be up to 50EMHz. For MCNS and DAVIC standards 44 MHz and 36 MHz are the two typical IF frequencies used. For 44EMHz the corresponding bandwidth is 6 MHz; for 36EMHz the corresponding bandwidth is 8 MHz. Sampling of the input may be set for 25 MHz for the 6EMHz bandwidth or 29 MHz for the 8 MHz bandwidth. The downstream receiver offers 16/64/256 QAM demodulation for Annex A, associated with DAVIC, or Annex B, associated with MCNS. It also offers a variety of choices for the data and clock outputs: frames with or without gaps and parallel or serial data. The incoming signal is sampled. The timing recovery circuit determines the epoch of each symbol. Automatic frequency and gain control circuitry correct the frequency and amplitude of the signal, and a Digital Down Converter (DDC) brings the alias band associated with sampling down to zero. A Nyquist filter eliminates inter-symbol interference, and an Adaptive Channel Equalizer (ACE) corrects for channel distortion while fine tuning the signal. A demapper transforms the modulated signal back into symbols and a De-
TRANSMITTER OVERVIEW
The transmitter is highly integrated and flexible. It receives serial data, randomizes the data, performs Forward Error Correction (FEC) and differential encoding, maps the data to a constellation before modulation, and outputs an analog RF signal. It includes a 10-bit DAC and is capable of operating at data rates up to 20 Mbps in QPSK mode and 40EMbps in 16QAM mode. The transmitter uses a digital FIR filter to optimally shape the spectrum of the modulating data prior to modulation. Signal level scaling is provided after the FIR filter to allow maximum arithmetic dynamic range. The transmitter side offers QPSK and 16QAM modulation with frequencies from 5 to 65 MHz. It can operate in continuous or burst mode. And it can operate with very short gaps between bursts less than four symbols. All digital interfaces support 3.3 volt and 5 volt logic.
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Introduction
MECHANICAL SPECIFICATIONS
208-PIN SQFP PACKAGE
Dimensions are in millimeters.
TPG 53310. 29/97 c-7/
Table 1. STEL-2176 Pin Assignments
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Pin Name VSS VDD RXOSCIN RXOSCOUT VSS VDD VDDA RXMULTEN VSSA VSS RXMULTCLK VDD ADCDATASEL[2] ADCDATASEL[1] ADCDATASEL[0] VSS ADDATA[9] Pin Type Ground Power Input Output Ground Power Power (Analog) Input Ground (Analog) Ground Output Power Input Input Input Ground Bi-directional Pin Description Dedicated to crystal oscillator at pins 3 & 4 Receiver oscillator input Receiver oscillator output Dedicated to crystal oscillator at pins 3 & 4 Dedicated to digital section of receive clock multiplier Dedicated to analog section of receive clock multiplier Enable receive clock multiplier Dedicated to receive clock multiplier Dedicated to receive clock multiplier Receive clock multiplier output; enabled by pin 58 ADC/DAC bypass mode select; 111=normal operation ADC/DAC bypass mode select; 110=bypass ADC ADC/DAC bypass mode select; 101=bypass DAC Bypass/test ADC/DAC
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STEL-2176
Introduction
Pin No. 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name ADDATA[8] ADDATA[7] ADDATA[6] ADDATA[5] VDD ADDATA[4] ADDATA[3] ADDATA[2] ADDATA[1] ADDATA[0] VSS RXAGCOUTB RXAGCOUTA VDD5 V3OP VSS IC SO VDD SI SCK VSS ADDR[7] ADDR[6] ADDR[5] ADDR[4] VDD ADDR[3] ADDR[2] ADDR[1] ADDR[0] VSS INTSEL[1] INTSEL[0] VDD VSS Pin Type Bi-directional Bi-directional Bi-directional Bi-directional Power Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Ground Output Output Power Input Ground Output Power Input Input Ground Input Input Input Input Power Input Input Input Input Ground Input Input Power Ground Input Input Input Power Input Ground Bi-directional Bi-directional Bi-directional Bi-directional Power Bi-directional Bi-directional Bi-directional Bi-directional Ground Output Power Output Output Output Output Pin Description Bypass/test ADC/DAC Bypass/test ADC/DAC Bypass/test ADC/DAC Bypass/test ADC/DAC Bypass/test ADC/DAC Bypass/test ADC/DAC Bypass/test ADC/DAC Bypass/test ADC/DAC Bypass/test ADC/DAC AGC output B AGC output A 3.3V or 5V for AGC pins 29 & 30 Must set high if pin 31 is 3.3V or low if pin 31 is 5V Internal connection - leave open SPI data out SPI data in SPI clock Control/Status register parallel address bus Control/Status register parallel address bus Control/Status register parallel address bus Control/Status register parallel address bus Control/Status register parallel address bus Control/Status register parallel address bus Control/Status register parallel address bus Control/Status register parallel address bus Serial/parallel inter. sel.: 00=parallel, 01=SPI (serial) Serial/parallel interface select: 10=reserved, 11=res.
CS
Control/Status register chip select (active low) Control/Status register read/write (low=write) Control/Status register data strobe signal (active low) Enables output pins 11 & 102 Control/Status register parallel data in/out Control/Status register parallel data in/out Control/Status register parallel data in/out Control/Status register parallel data in/out Control/Status register parallel data in/out Control/Status register parallel data in/out Control/Status register parallel data in/out Control/Status register parallel data in/out FEC test clock output (8 times RX symbol rate) Test mux output Test mux output Test mux output Test mux output
WRB
DSB
VDD ENCLKOUT VSS DATA[7] DATA[6] DATA[5] DATA[4] VDD DATA[3] DATA[2] DATA[1] DATA[0] VSS RXRESCLK VDD RXTSTDOUT[9] RXTSTDOUT[8] RXTSTDOUT[7] RXTSTDOUT[6]
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Introduction
Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 Pin Name VSS RXTSTDOUT[5] RXTSTDOUT[4] RXTSTDOUT[3] RXTSTDOUT[2] VDD RXTSTDOUT[1] RXTSTDOUT[0] RXTSTCLK VSS VDD VDDA DACOUTP DACOUTN VSSA VSS VDD TXOSCIN TXOSCOUT VSS VDD VDDA TXPLLEN VSSA TXBYPCLK VDD TXPLLCLK VSS VDD VSS Pin Type Ground Output Output Output Output Power Output Output Output Ground Power Power (analog) Analog output Analog output Power (analog) Ground Power Input Output Ground Power Power (analog) Input Ground (analog) Input Power Output Ground Power Ground Input Power Input Input Input Ground Input Input Power Input Input Input Input Ground Output Output Output Power Output Output Input Power Input Ground Output Output Output Pin Description Test mux output Test mux output Test mux output Test mux output Test mux output Test mux output Test mux output clock Dedicated to digital portion of DAC Dedicated to analog portion of DAC Output of DAC. Terminate in 37.5 ohms to ground (See Figure 2) Comp. output of DAC. Terminate in 37.5 ohms to ground (See
Figure 2)
Dedicated to analog portion of DAC Dedicated to digital portion of DAC Dedicated to crystal oscillator at pins 93 & 94 TX oscillator input TX oscillator output Dedicated to crystal oscillator at pins 93 & 94 Dedicated to digital section of transmit clock PLL Dedicated to analog section of transmit clock PLL Enable transmit clock PLL Dedicated to analog section of transmit clock PLL High speed transmit bypass clock Dedicated to digital section of transmit clock PLL Transmit clock PLL output; enabled by pin 58 Dedicated to digital section of transmit clock PLL
TXRSTB
VDD TXTSDATA TXDATAENI TXTCLK VSS TXFCWSEL[1] TXFCWSEL[0] VDD TXCLKEN TXDIFFEN TXRDSLEN TXSCRMEN VSS TXCKSUM TXACLK TXDATAENO VDD TXBITCLK TXSYMPLS TXNCOLD VDD5 RXRSTB VSS RXPDATAOUT[7] RXPDATAOUT[6] RXPDATAOUT[5]
Transmit reset (active low) Transmit data input Transmit data enable input Transmit tclk Transmit frequency control word (FCW) select Transmit frequency control word (FCW) select Transmit clock enable Transmit differential encoder enable Transmit Reed-Solomon enable Transmit scrambler enable Transmit Reed-Solomon check sum Transmit auxiliary clock output Transmit data enable output Transmit bit clock Transmit symbol pulse output Transmit NCO load Input buffer bias. Set to 3.3V or 5V dep. on max. input V. voltage. Receiver reset (active low) Receive parallel output data Receive parallel output data Receive parallel output data
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Introduction
Pin No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 Pin Name RXPDATAOUT[4] VDD RXPDATAOUT[3] RXPDATAOUT[2] RXPDATAOUT[1] RXPDATAOUT[0] VSS RXOUTCLK VDD RXACQFLAG RXACQFAIL RXDECDFLG FRAMESYNC VSS SRAMADDR[15] SRAMADDR[14] SRAMADDR[13] SRAMADDR[12] VDD SRAMADDR[11] SRAMADDR[10] SRAMADDR[9] SRAMADDR[8] VSS VDD VSS SRAMADDR[7] SRAMADDR[6] SRAMADDR[5] SRAMADDR[4] VDD SRAMADDR[3] SRAMADDR[2] SRAMADDR[1] SRAMADDR[0] VSS SRAMDATA[7] SRAMDATA[6] SRAMDATA[5] SRAMDATA[4] VDD SRAMDATA[3] SRAMDATA[2] SRAMDATA[1] SRAMDATA[0] VSS SRAMWEB SRAMCSB SRAMOEB VDD RXIENBLE RXQENBLE VSS RXBYPCLK VDD VSSA VDDA VCMA VDD Pin Type Output Power Output Output Output Output Ground Output Power Output Output Output Output Ground Output Output Output Output Power Output Output Output Output Ground Power Ground Output Output Output Output Power Output Output Output Output Ground Bi-Directional Bi-Directional Bi-Directional Bi-Directional Power Bi-Directional Bi-Directional Bi-Directional Bi-Directional Ground Output Output Output Power Input Input Ground Bi-directional Power Ground (analog) Power (analog) Analog output Power Pin Description Receive parallel output data Receive parallel output data Receive parallel output data Receive parallel output data Rec. par. output data or serial data if in serial mode Receive output data clock Receive demod. acquisition flag Receive demod. acquisition failure flag Receive FEC decodable flag Receive output frame sync flag De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address
De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM address De-Interleaver optional external SRAM data bus De-Interleaver optional external SRAM data bus De-Interleaver optional external SRAM data bus De-Interleaver optional external SRAM data bus De-Interleaver optional external SRAM data bus De-Interleaver optional external SRAM data bus De-Interleaver optional external SRAM data bus De-Interleaver optional external SRAM data bus De-Interleaver SRAM write enable (active low) De-Interleaver SRAM chip select (active low) De-Interleaver SRAM output enable (active low) FEC test input I clock FEC test input Q clock Receiver bypass clock input; output reserved Dedicated to analog section of ADC (See Figure 1) Dedicated to analog section of ADC (See Figure 1) From ADC (See Figure 1) Dedicated to digital section of ADC (See Figure 1)
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Introduction
Pin No. 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 Pin Name VREFN VSSA VSS VDDA VDDA ADCINP ADCINN VSSA VSSA VDD VDDA VREFP VSS VCMB VSSA VDDA VDD Pin Type Analog output Ground (analog) Ground Power (analog) Power (analog) Analog input Analog input Ground (analog) Ground (analog) Power Power (analog) Analog output Ground Analog output Ground (analog) Power (analog) Power Pin Description From ADC(See Figure 1) Dedicated to analog section of ADC (See Figure 1) Dedicated to digital section of ADC (See Figure 1) Dedicated to analog section of ADC (See Figure 1) Dedicated to analog section of ADC (See Figure 1) ADC input(See Figure 1) Complementary ADC input (See Figure 1) Dedicated to analog section of ADC (See Figure 1) Dedicated to analog section of ADC (See Figure 1) Dedicated to digital section of ADC (See Figure 1) Dedicated to analog section of ADC (See Figure 1) From ADC(See Figure 1) Dedicated to digital section of ADC (See Figure 1) From ADC(See Figure 1) Dedicated to analog section of ADC (See Figure 1) Dedicated to analog section of ADC (See Figure 1)
Digital GND (VSS) Analog In (N) Analog In (P) Analog GND (VSSA)
0.1 F
0.1 0.1 F F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
0.1 F
Digital Supply (VDD)
STEL-2176
Figure 1. Reference A/D Wiring
T1-6TKK81
0.1 F DACOUTP 50 AVSS 0.1 F DACOUTN 50 AVSS
0.1 F
50 line
Note 1 50 load
X
MiniCircuits 1:1
Note 1: Normally some application dependent alias filtering and amplitude control appear at this point in the circuit
WCP 53807.c-12/5/97
Figure 2. Example Output Load Schematic User Manual
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STEL-2176
Introduction
ELECTRICAL SPECIFICATIONS
The STEL-2176 electrical characteristics are provided by Table 2 through Table 4.
WARNING
Stresses greater than those shown in Table 2 may cause permanent damage to the STEL-2176. Exposure to these conditions for extended periods may also affect the STEL-2176 reliability.
Table 2. Absolute Maximum Ratings
Symbol T stg VDDmax AVDDmax 5VDDmax AV SS VI(max) Ii PDiss (max) Parameter Storage Temperature Supply voltage on VDD Supply voltage on AVDD Supply voltage on 5VDD Analog supply return for AVDD Input voltage DC input current Power dissipation Range 40 to +125 0.3 to +4.6 0.3 to +4.6 0.3 to +7.0 10% of VDD 0.3 to 5VDD+0.3 30 1500 Units Note 1 C volts volts volts Note 2 volts volts mA mW
Note: All voltages are referenced to VSS. 5VDD must be greater than or equal to VSS. This rule can be violated for a maximum of 100 msec during power up.
Table 3. Recommended Operating Conditions
Symbol AV DD 5VDD VDD CLOAD RLOAD VLOAD Ta Parameter Supply Voltage Supply Voltage Supply Voltage DAC Load Capacitance DAC Load Resistance Recommended DAC Load DAC Output Voltage Operating Temperature (Ambient) Range +3.3 10% +5.0 10% +3.3 10% 20 30K 37.5 1.25 40 to +85 Units Note 1 Volts Volts Note 2 Volts pF ohms ohms Volts C Note 3
Note: 1. All voltages with respect to V SS and assume AVss = Vss 2. 3. If interface logic is to be driven by VDD then connect the 5VDD pin to the V DD supply and set pin 32 to correct value. Duty Cycle Derating is required from +70 to +85 C.
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Introduction
Table 4. ADC Performance Specifications
Parameter Sampling Frequency Resolution Input Differential Signal Range Analog Input Bandwidth Signal to Distortion Ratio 10 MHz signal over 25 MHz BW Input Common Mode 1.4 1.5 1.6 Volts -0.75 60 54 10 +0.75 Min Nom Max 50 Units MHz bits Volts MHz dB
Table 5. DC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = -40 to 85 C)
Symbol IVDDQ IVDD I5VDD IAV DD VIHCLK VILCLK VIH VIL IIH IIL Parameter Supply Current, Quiescent Supply Current, Operational, VDD Supply Current, Operational, 5VDD Supply Current, Operational, AVDD Clock High Level Input Voltage Clock Low Level Input Voltage High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current 2.4 3.0 0.2 40 2 4 16 19 0.96 N/A 4 8 pF 10 22 2.0 0.8 10 10 VDD 0.4 2.0 0.8 Min. Nom. 1.9 0.2 12.0 Max. 1.0 Units mA mA/MHz mA mA volts volts volts volts A A volts volts mA pF pF mA Volts CLK, Logic '1' CLK, Logic '0' Other inputs, Logic '1' Other inputs, Logic '0' VIN = 5V DD VIN = VSS IO = 2.0 mA IO = +2.0 mA VOUT = VDD, VDDE=Emax All inputs All outputs Single output Based on 50 ohms load resistance to ground. Conditions Static, no clock
VOH(min) High Level Output Voltage VOL(max) Low Level Output Voltage IOS CIN COUT IOFS VO RO CO Output Short Circuit CurrentE Input Capacitance Output Capacitance Output Full Scale DAC Current DAC Compliance Voltage (Differential) DAC Output Resistance DAC Output Capacitance
1
NOTES: 1. Current source to ground output.
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STEL-2176
Receiver Description
RECEIVER
OVERVIEW
The STEL-2176 is a complete subscriber-side cable modem ASIC which integrates both the downstream receiver and upstream transmitter functions. The receiver includes a high performance 10-bit Analog-toDigital Converter (ADC) with a direct Intermediate Frequency (IF) interface. The receiver also includes a QAM demodulator and both ITU-T (J.83) Annex A and Annex B Forward Error Correction (FEC). The upstream transmitter includes a BPSK/QPSK/16QAM modulator with highly flexible FEC and scrambling, and a 10-bit low spurious digital to analog converter (DAC) for direct synthesis of an upstream 5 to 65 MHz signal. Both the receiver and transmitter are highly flexible and programmable; the STEL-2176 Digital Mod/Demod ASIC offers a solution to meet current and evolving standards. The input to the STEL-2176 receiver is an analog IF signal of up to 50 MHz. Typically, the IF signal has 44 MHz center frequency with a 6 MHz bandwidth for NTSC based systems, or a 36 MHz center frequency with an 8 MHz bandwidth for PAL based systems. In typical applications, the input signal is sampled by the ADC at approximately 25 MHz for the 44 MHz IF, or at approximately 29 MHz for the 36 MHz IF This type of sub-sampling technique works by intentionally undersampling the carrier frequency so that aliased signal appears at a lower frequency. The sampling rate is still high enough to capture all of the modulation bandwidth without distortion. In the case of a 44 MHz IF and a 25 MHz clock, the resulting digital signal is centered at 6 MHz. In the case of a 36 MHz IF and 29 MHz clock, the resulting digital signal is centered at 7 MHz. For more information on subsampling techniques, please see Stanford Telecom Application Note A-117. The digital samples from the ADC are downconverted to baseband I and Q signals in the Digital Down Converter (DDC) block. Since the RF tuner sections of a cable modem may have large frequency errors, an Automatic Frequency Control (AFC) block is used in the STEL-2176 for coarse tuning of the DDC. This allows rapid acquisition of the input signal even with frequency errors of 200 kHz. Fine tuning of the DDC is done using a carrier Phase-Lock Loop (PLL). An Automatic Gain Control (AGC) function provides two output signals to adjust the RF and IF analog gain stages of circuitry external to the STEL-2176, so that the ADC input is in the optimal range. The two outputs can be programmed to create a sequential AGC system which maximizes RF gain for improved receiver noise figure. The two AGC outputs and the external gain adjust blocks work together to maximize ADC performance, but when large adjacent channels are present, the power of the desired signal may change. A second digital AGC tracks and adjusts the level of the desired signal after the adjacent channel energy is removed by filtering. Following the DDC, a square root raised cosine Nyquist filter eliminates adjacent channel signals, and performs matched filtering to eliminate intersymbol interference. The filter excess bandwidth or alpha is programmable from 0.12 to 0.20. The Timing Recovery block finds the exact location in the center of each symbol using a special low-jitter discriminator. These values are fed to the Adaptive Channel Equalizer. An Adaptive Channel Equalizer (ACE) compensates for any multipath distortion on the input signal introduced in the channel. The equalizer uses one sample per symbol (T spaced taps). The output of the equalizer is baseband I and Q signals with carrier frequency and phase errors, symbol timing errors, gain errors, and multipath effects removed. The Demapper takes the baseband I and Q signals representing the QAM symbols, and translates each symbol back into a series of binary values based on one of the selectable constellation maps. Following the Demapper is the Forward Error Correction (FEC) system. This programmable system supports both the ITU-T (J.83) Annex A (see page 14) and Annex B (see page 16) standards. In general, both FEC systems employ Reed Solomon Decoders, Frame Sync circuits that determine the FEC code block boundaries, and a De-Interleaver. Interleaving is used in the FEC standards to improve performance when the channel contains bursty noise. Since the transmitter Interleaver spreads the data over a large time, when the receiver performs the matched operation to the Interleaver in order to bring the data back into the correct time sequence, any burst errors appear to be spread out in time. This helps makes these errors
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User Manual
Receiver Description correctable by the FEC. The STEL-2176 internal memory can support all MCNS Interleaver configurations. For deeper interleaving, a direct interface to external memory is provided. The output of the receiver is typically arranged as MPEG-2 frames, although the MPEG-2 framing can be by-passed for ATM applications. The output can be 8bit parallel with a byte clock or serial with a bit clock. The data can be output in a smooth fashion without inter-frame gaps or with the pauses in output data caused by the FEC system passed through to the output (see Receiver Timing discussion).
1st IF Output 44 MHz 36 MHz
Fo=44/36 MHz BW= 6/8 MHz A
4Samples/Symbol
Interpolator
A
ADC
AFC AGC DDC
Programmable Nyquist (0.12 to 0.2)
Clock Recovery
Adaptive Channel Equalizer (20 taps)
De-mapper Viterbi Diff. Decoder
10 bits/ ~25 MHz Sample
Reed-Solomon Decoder (204,188 and 128,122)
Micro Controller Interface
Clock Synthesizer
Frame Sync
Deinterleaver
Micro Controller ( SPI, Parallel)
~25 MHz XO
External RAM
WCP 52861.c-5/07/97
Figure 3. STEL-2176 Receiver Block Diagram
FUNCTIONAL BLOCKS
ADC The ADC uses differential analog signal inputs ADCINP and ADCINN. Differential coupling to the ADC is important to prevent common mode noise from the digital sections of the ASIC from coupling into the input. The recommended input signal level is 0.75V. The input is sampled by the ADC, and the samples are converted into 10-bit digital values. The sampling rate is typically 25 MHz for an input of 44 MHz 3 MHz with a symbol rate of about 5 MHz (i.e., the MCNS standard) or 29 MHz for an input of 36 MHz 4 MHz with a symbol rate of about 7 MHz (i.e., the DAVIC and DVB standards). The sampling rate is controlled the choice of crystal connected between RXOSCIN and RXOSCOUT or by the clock frequency applied to User Manual RXOSCIN. The sample rate must be slightly more than 4 samples per symbol. The sample clock generated by the crystal/receive clock oscillator or applied to RXOSCIN must be a low phase noise signal. For this reason, dedicated power and ground connections for the receive oscillator and input buffer are adjacent to the RXOSCIN and RXOSCOUT pins. Microcontroller Interface The microcontroller interface provides access to the internal programmable Universal, Downstream (Receive), and Upstream (Transmit) registers (see page 20) via a parallel or a SPI interface. The interface used is selected by the interface select lines (INTSEL[1-0]).
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STEL-2176
Receiver Description
The parallel interface consists of an 8-bit address bus (ADDR[7-0]), an 8-bit bi-directional data bus (DATA[70]), and the control signals chip select (CS), read/write (WRB), and data strobe (DSB). The SPI interface consists of a serial input (SI), serial output (SO), and a serial clock (SCK). Master Receive Clock Generator The STEL-2176 uses a master clock (MCLK) to control the receive timing functions. MCLK can be generated in either of three ways as shown in Figure 4. A receive bypass clock can be applied to the RXBYPCLK input and selected to drive CLK. The RXMULTEN should be held high to select the RXBYPCLK input. An external clock can be applied to the RXOSCIN input or a crystal can be connected across the RXOSCIN and RXOSCOUT inputs. The oscillator circuit outputs a 2050 MHz signal to a frequency multiplier PLL, which upconverts the signal to a 100-150 MHz clock. When the bypass clock is not used, RXMULTEN is driven high to
select the output of the frequency multiplier to drive the MCLK signal. The frequency multiplier output frequency is controlled by the formula: MCLK=OscillatorOutput where: * * The Oscillator signal (RXOSCIN and RXOSCOUT) is four times the signal symbol rate. The value of M and N should be selected so MCLK is four times the value of the Oscillator signal. N is the value stored in RxFsynN (bits 6-0 of Bank 0 Register F7 H), and M is the value stored in RxFsynM (bits 6-0 of Bank 0 Register F6 H). The recommended values for DAVIC, DVB, and IEEE 802.14 are Oscillator Frequency = 29 MHz, M = 2, and N = 8. The recommended values for MCNS are Oscillator Frequency = 25 MHz, M = 2, and N = 8. N M
*
*
ENCLKOUT RXMULTCLK To ADC OSCILLATOR RXOSCIN FREQUENCY MULTIPLIER PLL MUX MCLK
RXOSCOUT RXMULTEN RXBYPCLK RXBYPASSFSYN
WCP 53852.c-12/7/97
Figure 4. Master Receive Clock Generator
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Receiver Description QAM Demodulator Blocks The following diagram shows the major QAM circuit blocks. The complex NCO drives a pair of multipliers which serve as mixers. The products of the ADC samples and the sine and cosine outputs of the NCO produce the desired baseband I and Q signals plus undesired higher frequency image terms. These higher frequency terms are removed by an image filter. Automatic Frequency control (AFC)
I,Q (1 sample/ Timing Recovery symbol) & SRRC Filter I,Q (to FEC)
OutA
OutB
AGC
S(t)
ADC
DDC I,Q
Adaptive Equalize
AFC
WCP 53702.c-10/28/97
The STEL-2176 can accommodate up to 200 kHz uncertainty in the carrier frequency. The carrier frequency recovery is divided into two steps. The first step is a coarse frequency estimation during initial signal acquisition. This estimation is performed by the AFC section. The estimated carrier frequency offset is calculated by the AFC and fed to the DDC NCO. AGC The AGC takes the output from the Image Filter in the DDC and estimates the power of the signal. The AGC discriminator compares the estimate to one or two different thresholds that can be set via the registers values AGC_ThresholdA (Bank 0 Register 14 H ) and AGC_ThresholdB (Bank 0 Register 15H). Thresholds should be set to optimize ADC performance. The range of the AGCs power thresholds is 0 to 128 (2 8-1). For 256QAM, the value ranges from about 75 to 100 (default is 96), depending on the desired A/D clipping level. The trade off for selecting the value weighs occasional ADC clipping with a large input versus loss of signal fidelity with a small input. The power of the input signal depends upon adjacent channel interference, AM hum, burst noise, etc. The AGC generates two 1-bit outputs OUTA and OUTB that indicate whether that the input analog signal is too high or too low. The OUTA and OUTB signals should be smoothed using low pass filters. These filters can each be a series resistor of ___ ohms and a shunt capacitor of ___ _ F. OUTA and OUTB can be set to have a logic high voltage of either 3.3V or 5V. For 3.3V operation, connect the power source's +3.3V output to pins 31 and 32 and its return to VSS. For 5V operation, connect the power source's +5V output to pin 31 and its return to pin 32 and VSS. The polarity of OUTA and OUTB may be controlled with AGC_InvertOutputA (bit 0 of Bank 0 Register 12H ) and AGC_InvertOutputB (bit 1 of Bank 0 Register 12H). For variable gain stages where a higher control voltage at the input to the filter produces higher gain, set the AGC_InvertOutput bit to 0. For variable gain stages
Figure 5. QAM Demodulator Blocks Digital Down Converter (DDC) The digital samples from the ADC are mixed down to baseband I and Q signals in the Digital Down Converter (DDC) block. The input analog signal is subsampled at the rate set by the receive crystal oscillator or a clock applied directly to the RXOSCIN input. The resultant sub-sampled input signalOs spectrum is aliased to a lower frequency. In typical cases, with a 44 MHz _ 3 MHz input and a 25 MHz sample rate, the digital signal appears to the input of the DDC as a 6 MHz _ 3 MHz signal. For a 36 MHz _ 4 MHz input and a 29 MHz sample rate, the digital signal appears to the input of the DDC as a 7 MHz _ 4 MHz signal. Other input frequencies and sample rates are also possible. The digital signal is down converted to baseband I and Q by mixing with cos 2 fc t and sin 2 f c t where fc is the center frequency of the digital signal. The Digital Down Converter contains a numerically controlled oscillator (NCO) with cosine and sine outputs, a pair of mixers, and an image filter. The frequency fc is a combination of a starting value that is set using DeltaTheta_in [13:0] (bits 7-2 of Bank 0 Register 10H and Bank 0 Register 11H ) and any frequency error terms computed by the Automatic Frequency Control block. The value for DeltaTheta_in [13:0] is given by: DeltaTheta_in [13:0] = fc /ADC sample rate _214 For fc = 6 MHz and ADC sample rate = 25 MHz, DeltaTheta_in [13:0] = 0F5CH For fc = 7 MHz and ADC sample rate = 29 MHz, DeltaTheta_in [13:0] = 0F73H User Manual
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STEL-2176
Receiver Description where a higher control voltage at the input to the filter produces lower gain, set the AGC_InvertOutput bit to 1. The two outputs can be programmed to create a sequential AGC system which maximizes RF gain for improved receiver noise figure. This is accomplished by setting AGC_ThresholdA (Bank 0 Register 14H ) and AGC_ThresholdB (Bank 0 Register 15H ) to slightly different values. The threshold which is set to a lower value will cause its associated output to command increase gain first. This output is typically connected to the RF variable gain stages so that the best receiver noise figure is achieved. Timing Recovery and Nyquist Filter The sampled signal (> 4 times the symbol rate in I and Q format) is fed to this block to: Eliminate inter-symbol interference (ISI) by filtering it with a square route raised cosine filter (SRRC) of a selectable excess bandwidth (a) for 12%<= a<=20%. Recover the exact symbol rate, within 100 ppm of the nominal value. Resample and transmit one composite sample (I and Q for each symbol) to the equalizer. These samples are taken at the epoch of each symbol. Adaptive Channel Equalizer The output of the Timing Recovery block is fed to the Adaptive Equalizer at a rate of one complex sample/symbol. The Adaptive Equalizer will: 1. Compensate for channel distortion including: a. c. 2. 3. 4. Multipath FM hum b. AM hum d. Phase noise Fine tune to the carrier frequency and phase offset. Set the acquisition flag OtrueO, after the equalizer successfully locks on to the signal. Write to ErrPwr (Block 0 Register 44H) the estimated output SNR.
Demapper
The adaptive equalizer control registers are Block 1 Registers 21H to 24H. FEC Decoder Blocks The purpose of the FEC subsystem is to improve the bit error rate performance of the data link. The arrangement of the FEC blocks in the receiver is in reverse order from the transmitter. The STEL-2176 FEC subsystem can decode signals which are generated in conformance with either the ITU-T (J.83) Annex A or Annex B FEC standards. There are two different though similar set of blocks used for ITU-T (J.83) Annex A (Figure 6) and Annex B (Figure 13). The STEL-2176 supports the MPEG-2 standard. MPEG-2 uses 188 byte packets with a sync byte and three header bytes containing service identification, scrambling, and control information. The 184 bytes of data follows the sync and header bytes. Normally this header information flows through to the receiver output, but with ITU-T (J.83) Annex B there is an option of bypassing the MPEG-2 outer layer of processing. Annex A FEC The ITU-T (J.83) Annex A FEC subsystem consists of the following blocks:
I,Q from Adaptive Equalizer
De-mapper
Frame Sync
De-Interleaver
Reed-Solomon Decoder
De-Randomizer
To Output Clock
WCP 53703.c-10/28/97
Figure 6. ITU-T (J.83) Annex A FEC Subsystem
This block maps the Adaptive Channel Equalizer I and Q outputs for each symbol into 4, 6, or 8 bits for 16, 64, or 256 QAM respectively. The mapping tables are as follows:
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Receiver Description
Q
Q
000100 001100 011100 010100 110100 111100 101100 100100
11
01
10
11
000101
001101
011101 010101
110101
111101
101101
100101
000111
001111
011111 010111
110111
111111
101111
100111
IkQk=00
IkQk=10
10 00 00
IkQk=00
01
000110
001110
011110 010110
110110
111110
101110
100110
000010
001010
011010 010010
110010
111010
101010
100010
000011
001011
011011 010011
110011
111011
101011
100011
I
rotate 90 degrees
000001
001001
011001 010001
110001
111001
101001
100001
01
00
00
10
000000
001000
011000 010000
110000
111000
101000
100000
IkQk=10
I I I I I I I I I I I I I I I I
rotate 180 degrees
rotate 270 degrees IkQk=01
WCP 53713.c-10/29/97
IkQk=11
11 10 01
IkQk=01
11
WCP 53711.c-10/29/97
IkQk=11
Figure 9. 256 QAM Constellation (DAVIC)
Q
Figure 7. 16 QAM Constellation
Q
1100 1110 0110 0100 1000 1001 1101 1100
100000
100001
100101
100100
110100
110101
110001
110000
100010
100011
100111
100110
110110
100111
110011
110010
101010
101011
100111
101110
111110
111111
111011
111010
IkQk=00
1101 1111 0111 0101 1010 1011 1111 1110
IkQk=10
1001 1011 0011 0001 0010 0011 0111 0110 1000 1010 0010 0000 0000 0001 0101 0100
IkQk=00
101000
101001
101101
101100
111100
111101
111001
111000
001000
001001
001101
001100
011100
011101
011001
011000
001010
001011
001111
001110
011110
011111
011011
011010
I
0100
I
I
0101
I
I
0001
I
I
0000
I
0000
I
I
0010
I
I
1010
I
I
1000
I
000010 000011 000111 000110 010110 010111 010011 010010
rotate 90 degrees
000000 000001 000101 000100 010100 010101 010001 010000
0110
0111
0011
0010
0001
0011
1011
1001
IkQk=10
IkQk=11
1110
1111
1011
1010
0101
0111
1111
1101
IkQk=01
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
rotate 180 degrees IkQk=11
rotate 270 degrees IkQk=01
WCP 53839.c-12/5/97
1100
1101
1001
1000
0100
0110
1110
1100 WCP 53712.c-10/29/97
Figure 8. 64 QAM Constellation Two bits are the same for each modulation type, and are identified as I KQK. The remaining bits are identified as [bq-1 . . . bo], where q = 2, 4, and 6 for 16, 64 or 256 QAM. IKQK are processed by the differential decoder before being fed to the frame sync block. The remaining bits [bq-1 . . . bo] are fed directly to the frame sync.
Differential Decoder
Figure 10. 256 QAM Constellation (DVB/IEEE 802.14) b q+1= Ak = (Ik Ik-1) (Ik-1 Qk-1 ) (1Ik Qk) b q = Bk = (Qk Qk-1 ) (Ik-1 Qk-1 ) (1Ik Qk)
I Demapper Q Qk Ik Differential Decoder Q bits (bq-1... b0) Bk=bq Ak=bq+1 M-tuple to Byte Conversion To Frame Sync
WCP 53708.c-10/28/97
Two bits (IKQK) of each symbol are differentially decoded according to the equation: User Manual
Figure 11. Demapper
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STEL-2176
Receiver Description
Frame Sync
The frame sync receives symbols from the mapper. Each symbol represents 4, 6 or 8 bits for 16 QAM, 64 QAM, and 256 QAM respectively. These bits are collected into bytes. For 16 QAM, every two symbols are converted into one byte. For 64 QAM, every 4 symbols to are converted into 3 bytes, and for 256 QAM each symbol gives one byte.. Once bytes are formed, the frame sync block looks for a sequence of fixed byte values separated by 203 bytes of data. 47H (203 bytes) B8H (203 bytes) 47H (203 bytes) 47 H (203 bytes) 47H . . . 47H . . . 47H . . . . 47H . . 47H . . . 47H . . . B8H . . . When the frame sync finds this pattern HIT (Block 1 Register 55H) times, the frame sync block declares OacquisitionO and starts feeding the bytes to the DeInterleaver. The frame sync stays in the OacquisitionO state until it misses this pattern MISS (Block 1 Register 56H) times.
De-Interleaver
followed by 16 bytes of checksum. The code blocks are assumed to be coded according to ITU-T (J.83) Annex A FEC shortened R-S algorithm. If the decoder fails to decode a code block, the decoder sets the undecodable flag OtrueO for this block. This flag propagates to the STEL-2176 output as RXDECDFLG. In addition, the number of errors in each decodable block accumulates in Error_cnt[15:0] (Block 1 Registers 72H and 73H). This register can be reset by writing a 1 to CLR_ERR (bit 0 of Block 1 Register 74H).
De-Randomizer
The de-randomizer is exactly the same as the randomizer described by the ITU-T (J.83) Annex A standard.
Output Clock Block
This block is a convolutional De-Interleaver, as shown:
1 1 2 I-4 Input I-3 I-2 I-1 I
WCP 53704.c-10/28/97
2 J J J J J J
3 J J J J J J
4 J J J
I-2 J J
I-1 J
The function of the output clock block is to evenly distribute the output receive data of the STEL-2176 and to eliminate gaps caused by the FEC subsystem. The output of the Reed-Solomon decoder is 188 bytes of data for every 204 input bytes. Therefore, there is a gap of 16 bytes where the checksum information is removed. The STEL-2176 output can send the received data in bytes on an 8-bit wide buss, or in bits on a single line as shown in Downstream Output Timing Diagrams (Figure 19 through Figure 21). Selecting between ObytewiseO versus ObitwiseO can be done by setting Serial Mode (bit 0 of Bank 1 Register 69H) to 1. ANNEX B The ITU-T (J.83) Annex B FEC subsystem consists of the following blocks:
I,Q from Adaptive Equalizer
J J J J J J
Output J J J
Figure 12. De-Interleaver I and J are programmable (Block 1 Registers 47H and 48H). A total memory of J _ (I-1) _ I/2 is required. The STEL2176 has 8K internal memory. Up to 64K memory can be added externally without any additional logic, as shown.
Reed-Solomon Decoder
Trellis Coded De-modulator
Frame Sync
De-Randomizer
De-Interleaver
Reed-Solomon Decoder
MPEG-2 Framing
To Output Clock
WCP 53705.c-10/28/97
Figure 13. ITU-T (J.83) Annex B FEC Subsystem This function decodes Reed-Solomon blocks. Each code block is 204 bytes long and contains 188 bytes of data
STEL-2176
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Receiver Description
Cq Cq/2+1 Cq/2-1 I, Q Demapping C2 C1 Cq/2 C0 1/2 Binary Convolutional Decoder (4/5) punctured X Differential Y Decoder W Z Buffer 28 bits (64QAM) 38 bits (256 QAM) Frame Sync
WCP 53706.c-10/28/97
Figure 14. Trellis Coded Demodulator The demapping block maps the Adaptive Channel Equalizer I and Q outputs for each symbol into 4, 6, or 8
Q C5C4C3,C2C1C0
bits for 16, 64, or 256 QAM respectively. The mapping tables are as follows:
110,111 111,011 010,111 011,011 100,101 101,111 110,101 111,111
110,100 111,000 010,100 011,000 100,000 101,010 110,000 111,010
100,111 101,011 000,100 001,011 000,101 001,111 010,101 011,111
100,100 101,000 000,100 001,000 000,000 001,010 010,000 011,010
I
010,011 011,001 000,011 001,001 000,001 001,101 100,001 101,101
010,110 011,100 000,110 001,100 000,010 001,110 100,010 101,110
110,011 111,001 100,011 101,001 010,001 011,101 110,001 111,101
110,110 111,100 100,110 101,100 010,010 011,110 110,010 111,110
WCP 53709.c-10/29/97
Figure 15. 64 QAM Mapping
User Manual
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STEL-2176
Receiver Description
Q
C 7 C6 C 5 C 4 C 3 C2 C 1 C 0
1110, 1111 1100, 1110 1010, 1111 1000, 1110 0110, 1111 0100, 1110 0010, 1111 0000, 1110 1110, 0001 1110, 0010 1110, 0101 1110, 0110 1110, 1001 1110, 1010 1110, 1101 1110, 1110 1111, 1101 1101, 1100 1011, 1101 1001, 1100 0111, 1101 0101, 1100 0011, 1101 0001, 1100 1101, 0001 1101, 0010 1101, 0101 1101, 0110 1101, 1001 1101, 1010 1101, 1101 1101, 1110 1110, 1011 1100, 1010 1010, 1011 1000, 1010 0110, 1011 0100, 1010 0010, 1011 0000, 1010 1010, 0001 1010, 0010 1010, 0101 1010, 0110 1010, 1001 1010, 1010 1010, 1101 1010, 1110 1111, 1001 1101, 1000 1011, 1001 1001, 1000 0111, 1001 0101, 1000 0011, 1001 0001, 1000 1001, 0001 1001, 0010 1001, 0101 1001, 0110 1001, 1001 1001, 1010 1001, 1101 1001, 1110 1110, 0111 1100, 0110 1010, 0111 1000, 0110 0110, 0111 0100, 0110 0010, 0111 0000, 0110 0110, 0001 0110, 0010 0110, 0101 0110, 0110 0110, 1001 0110, 1010 0110, 1101 0110, 1110 1111, 0101 1101, 0100 1011, 0101 1001, 0100 0111, 0101 0101, 0100 0011, 0101 0001, 0100 0101, 0001 0101, 0010 0101, 0101 0101, 0110 0101, 1001 0101, 1010 0101, 1101 0101, 1110 1110, 0011 1100, 0010 1010, 0011 1000, 0010 0110, 0011 0100, 0010 0010, 0011 0000, 0010 0010, 0001 0010, 0010 0010, 0101 0010, 0110 0010, 1001 0010, 1010 0010, 1101 0010, 1110 1111, 0001 1101, 0000 1011, 0001 1001, 0000 0111, 0001 0101, 0000 0011, 0001 0001, 0000 0001, 0001 0001, 0010 0001, 0101 0001, 0110 0001, 1001 0001, 1010 0001, 1101 0001, 1110 0000, 1111 0000, 1100 0000, 1011 0000, 1000 0000, 0111 0000, 0100 0000, 0011 0000, 0000 0000, 0001 0010, 0000 0100, 0001 0110, 0000 1000, 0001 1010, 0000 1100, 0001 1110, 0000 0011, 1111 0011, 1100 0011, 1011 0011, 1000 0011, 0111 0011, 0100 0011, 0011 0011, 0000 0001, 0011 0011, 0010 0101, 0011 0111, 0010 1001, 0011 1011, 0010 1101, 0011 1111, 0010 0100, 1111 0100, 1100 0100, 1011 0100, 1000 0100, 0111 0100, 0100 0100, 0011 0100, 0000 0000, 0101 0010, 0100 0100, 0101 0110, 0100 1000, 0101 1010, 0100 1100, 0101 1110, 0100 0111, 1111 0111, 1100 0111, 1011 0111, 1000 0111, 0111 0111, 0100 0111, 0011 0111, 0000 0001, 0111 0011, 0110 0101, 0111 0111, 0110 1001, 0111 1011, 0110 1101, 0111 1111, 0110 1000, 1111 1000, 1100 1000, 1011 1000, 1000 1000, 0111 1000, 0100 1000, 0011 1000, 0000 0000, 1001 0010, 1000 0100, 1001 0110, 1000 1000, 1001 1010, 1000 1100, 1001 1110, 1000 1011, 1111 1011, 1100 1011, 1011 1011, 1000 1011, 0111 1011, 0100 1011, 0011 1011, 0000 0001, 1011 0011, 1010 0101, 1011 0111, 1010 1001, 1011 1011, 1010 1101, 1011 1111, 1010 1100, 1111 1100, 1100 1100, 1011 1100, 1000 1100, 0111 1100, 0100 1100, 0011 1100, 0000 0000, 1101 0010, 1100 0100, 1101 0110, 1100 1000, 1101 1010, 1100 1100, 1101 1110, 1100 1111, 1111 1111, 1100 1111, 1011 1111, 1000 1111, 0111 1111, 0100 1111, 0011 1111, 0000 0001, 1111 0011, 1110 0101, 1111 0111, 1110 1001, 1111 1011, 1110 1101, 1111 1111, 1110
I
WCP 53710.c-10/29/97
Figure 16. 256 QAM Mapping The de-mapper generates OqO bits for each symbol where q = 6 for 64 QAM and q = 8 for 256 QAM. Two bits (b o and bq / 2 ) are processed by the binary convolutional decoder and the differential decoder. The remaining bits are passed directly to the output buffer.
Viterbi Decoder
decoder uses the following formula to produce its output: W k = (Xk X k-1 ) *(1 Xk-1 Y k-1 ) (Yk Y k-1 ) * (Xk-1 Yk-1 ) Z k = (Xk Yk-1 ) (Yk Yk-1 )
Buffer
The binary convolutional decoder is a 1:2 Viterbi decoder (4/5 punctured). For every 5 consecutive input b o or bq /2 bits, the Viterbi decoder produces only 4 output bits. With this type of punctured code there are 5 possibilities for synchronization. The synchronization can occur automatically, or under manual control using the programmable registers. Setting VitFeedBackEn (bit 4 of Bank 0 Register F4H) to 1 selects the automatic mode, while setting it to 0 selects the manual mode. In the manual mode, the decoder starts at any point in the puncturing sequence. To skip to the next state, write 1 to VitFeedBack (bit 7 of Bank 0, Register FCH).
Differential Decoder
The trellis coded demodulator buffer converts groups of 5 symbols into a bitstream (28 bits for 64 QAM, or 38 bits for 256 QAM) following Annex B convention.
Frame Sync
This block receives data from the buffer. The frame sync looks for Annex B frame sync patterns which are different for 64 QAM and 256 QAM. Also, the separation distance between successive patterns is different (60 R-S code words for 64 QAM and 88 R-S code words for 256 QAM). When the frame sync finds this pattern HIT (Bank 1 Register 55H) times, the frame sync block declares OacquisitionO and starts further processing of the data.
The two bit streams coming out of the Viterbi decoder are fed into the differential decoder. The differential STEL-2176
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Receiver Description The frame sync stays in the OacquisitionO state until it misses this pattern MISS (Bank 1 Register 56H) times. When in the "acquisition" state, the frame sync patterns are deleted, except the 4 bits identifying the interleaving parameters. These can be used by the DeInterleaver to automatically select the De-Interleaving parameters. The remaining data, that is all bits between frame syncs, are formed in 7-table bits symbols and passed to the derandomizer.
Derandomizer
A total memory of J _ (I-1) _ I/2 is required. The STEL2176 has 8K internal memory. Up to 64K memory can be added externally without any additional logic, as shown.
Reed-Solomon Decoder
This function decodes Reed-Solomon blocks. Each code block is 128 (7 bits symbols) long and contains 122 (7Ebits symbols) of data followed by 6 (7 bits symbols) of checksum. The code blocks are assumed to be coded according to ITU-T (J.83) Annex B FEC R-S algorithm. If the decoder fails to decode a code block, the decoder sets the undecodable flag OtrueO for this block. This flag propagates to the STEL-2176 RXDECDFLG output. In addition, the number of errors in each decodable block accumulates in Error_cnt[15:0] (Bank 1 Registers 72H and 73H). This register can be reset by writing a 1 to CLR_ERR (bit 0 of Bank 1 Register 74H).
MPEG Framing
The Derandomizer uses a linear feedback shift register as shown below. It works in GF (128). The delay elements are initialized at the beginning of each frame to 7FH, 7F H and 7FH.
Data In 7 7 z -1 z -1 z -1 7 Data Out
3
WCP 53707.c-10/29/97
Figure 17. Derandomizer
De-Interleaver
The R-S decoderOs output is serialized and fed through the ITU-T (J.83) Annex B MPEG-2 syndrome converter. The output of the syndrome generator is monitored for the pattern of 47H separated by 1496 bits. When OnO (n is a programmable number) successive occurrences of this pattern are found, MPEG-2 frame sync is declared. MPEG-2 packets are framed by converting every 8 bits into one byte. After declaring successful MPEG-2 frame sync, the absence of a valid code word at the expected location is indicated as a packet error. MPEG-2 framing can be bypassed if so selected. In this case, the output of the R-S decoder will be reformed into bytes starting at the beginning of each frame.
This block is a convolutional De-Interleaver, as shown:
1 1 2 I-4 Input I-3 I-2 I-1 I
WCP 53704.c-10/28/97
2 J J J J J J
3 J J J J J J
4 J J J
I-2 J J
I-1 J
J J J J J J
Output J J J
Output Clock Block
The output clock block functionally the same as the Annex A output clock block. However, the gaps between data bytes occur due to eliminating the R-S checksum symbols, the frame sync information, and the bits that were added to support Viterbi decoding.
Figure 18. De-Interleaver I and J (Bank 1 Registers 47 H and 48H) are programmable, however in Level II, the I and J values are determined by the 4-bit pattern of the frame sync.
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STEL-2176
Receiver Description
RECEIVE AND UNIVERSAL REGISTER DESCRIPTIONS
PROGRAMMING THE 2176 RECEIVE FUNCTIONS
The STEL-2176 has a combination of universal, receive and transmit registers. The registers are arranged as three banks of registers (Bank 0, Bank 1, and Bank 2). The Bank 0 registers are divided into Group 1 and Group 2 registers. The Bank 1 and 2 registers form separate groups (Groups 3 and 4 respectively). The Bank 0 and 1 registers (Groups 1, 2, and 3) are described by the following paragraphs. The Bank 2 registers (Group 4) are described in the Transmitter section (see page 54). The Bank/Group address, shown below, must be written to register location FFH to access the respective
Bank 0 0 1 2 Group 1 2 3 4 Group Name Universal Registers (Group 1) QAM Demodulator Registers Universal Registers (Group 2) Downstream FEC Registers Upstream, or transmitter, Registers Bank/Group Address (location FFH) 00H 00H 01H 02H
bank of registers. Register location FF H can be accessed from each register bank/group. The registers can be accessed using the Microcontroller Interface's parallel or serial interface (see page 11).
REGISTER DESCRIPTIONS
Bank 0 - Universal Registers (Group 1) The Universal Registers (Bank 0, Group 1) consist of three sets of registers: Read/Write (see Table 6), Readonly, and Write-only (see Table 7). The Read-only register set (Bank 0 Register F2) is for factory use only and not described by this User Manual.
Table 6. Read/Write Register Set
Address
F1H F4H Not Used
7
6
5
Not Used BypassMPE Gframe (write only) Not Used
4
3
FECTestMode (Bypass QAM)
2
1
0
VitFeedBackEn
Factory Use Only Program to 0H Factory Defined Value - 0H
F5H F6H F7H F8H F9H FA H FBH FD H FEH Not Used Not Used Not Used Not Used
Factory Defined Value - 2H RxFsynM RxFsynN TxFsynM TxFsynN Not Used
RxBypassFsyn
TxBypassFsyn
Not Used Not Used
Factory Use Only QAMAcquisitionMaxTries QAMEnable QAMType
FEC Type
Table 7. Write Only Registers:
Address
F3H
7
6
5
Not Used
4
3
2
1
Reset_OutputFIFO
0
Factory Defined Value - 0H QAM Start
FCH
VitFeedBack
Factory Defined Value - 0H
LoadRxM
LoadRxN
LoadTxM
LoadTxN
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Receiver Description Bank 0, Group 1 Register Data Field Descriptions BypassMPEGframe Factory Use Only FEC Type This data field is a write only register. Setting it to 1 will bypass MPEG framing. This data field is used by the factory and must be programmed to the value indicated above. Used to select the type of FEC encoding: 00 _ Annex A 01 _ Annex B 10 _ STel use only For test purposes, the QAM can be bypassed by setting the value to 1. Data is then fed directly to the FEC. Setting the value to 1 loads the value of RxFsynM into the Receiver frequency synthesizer. Setting the value to 1 loads the value of RxFsynN into the Receiver frequency synthesizer. Setting the value to 1 loads the value of TxFsynM into the Transmitter frequency synthesizer. Setting the value to 1 loads the value of TxFsynN into the Transmitter frequency synthesizer. Setting the value to 1 starts the QAM acquisition. The programmed value determines the number of acquisition tries the QAM makes before it declares an acquisition failure. The acquisition process will be restarted. QAMEnable must be set to 1 to enable the QAM circuitry, before programming QAM Start. Used to select 16, 64, or 256 QAM 00 _ 16 QAM 01 _ 64 QAM 10 _ 256 QAM Setting the value to 1 resets the FIFO of the output clock in case of overflow. Setting value to 1 bypasses the frequency synthesizer in the Master Receive Clock Generator. Value controls the Receiver Frequency Synthesizer output. Value controls the Receiver Frequency Synthesizer output. Setting value to 1 bypasses the frequency synthesizer in the Master Transmit Clock Generator. Value controls the Transmitter Frequency Synthesizer output. Value controls the Transmitter Frequency Synthesizer output. When use of Viterbi Decoder feedback is enabled, setting the value to 1 forces the Frame Sync circuit to begin shifting by one symbol and testing for the start of the symbol group. Once the search is externally initiated the value should be returned to 0. Setting the value to 1 enables the use of Viterbi Decoder feedback for using the VitFeedBack register to force the Frame Sync circuit to search for the start of the symbol group.
FECTestMode LoadRxM LoadRxN LoadTxM LoadTxN QAM Start QAMAcquisitionMaxTries QAMEnable QAMType
Reset_OutputFIFO RxBypassFsyn RxFsynM RxFsynN TxBypassFsyn TxFsynM TxFsynN VitFeedBack
VitFeedBackEn
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STEL-2176
Receiver Description Bank 0 - QAM Demodulator Registers Universal Registers (Group 2) The QAM Demodulator Registers Universal Registers are divided into 6 sub-groups of registers. Each subSub-Group
A B C D E F
group has two sets of registers: a Read/Write set which is used for control purposes, and a Read-only set for monitoring purposes. The sub-groups are:
Name
Control, address range DDC, Nyquist, AGC, and AFC address range Timing, address range FFE, address range FBE, address range PLL, address range
Read/Write Register Addresses
00H to 0EH 0FH to 1BH 1C H to 20H 21H to 24H 25H to 26H 27H to 3FH
Read-only Register Addresses
40H to 45H 46H to 52H 53H to 5BH 5C H to 5FH and 6BH to 9AH 9BH to B2H 60H to 6AH
Bank 0, Group 2, Sub-Group 'A' - Control Address Range Registers Table 8. Group 2, Sub-Group 'A' Read/Write Registers
Address
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0C H 0DH 0EH
7
6
5
Pwrlvl_corre ctEn
4
Decimate_Gai nSel
3
2
1
0
QAM_Enable QAM_SoftR esetEnable
Factory Defined Value - A H
Factory Defined Value - 19H Factory Defined Value - 44H Factory Defined Value - 19H CMA1_Ksym AFC1_Ksym CMA2_Ksym AFC2_Ksym Factory Defined Value - 64H Factory Defined Value - 00H Factory Defined Value - 00H Factory Defined Value - 64H Factory Defined Value - 40H = 16 QAM, 53H = 64 QAM, or 87 H = 256 QAM Factory Defined Value - 33H = 16 QAM, 37H = 64 QAM, or 54 H = 256 QAM Factory Defined Value - 5FH = 16 QAM, 76H = 64 QAM, or A4H = 256 QAM
Table 9. Sub-Group 'A' Read-Only Registers
Address
40H 41H 42H 43H 44H 45H
7
6
5
AcquisitionLock
4
AcquisitionFail SymbolCnt[9:2] SymbolKCnt AcquireCnt ErrPwr JitPwr
3
2
State
1
0
SymbolCnt[1:0]
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Receiver Description Bank 0, Group 2, Sub-Group 'A' Register Data Field Descriptions AcquireCnt AcquisitionFail AcquisitionLock Decimate_GainSel The value indicates the number of times the STEL-2176 has attempted to acquire the signal. The value is set to 1 when an acquisition failure is declared due to excessive error power; the STEL-2176 is also returned to the idle mode. The value is set to 1 when acquisition lock is detected. If GainSel is low (the default), the Nyquist filter output (10 bits plus 1 fractional bit) is multiplied by a factor of 1.25 (+2 dB power); if GainSel is high, the scale factor is 1.5 (+3.5 dB power). Provides an indication of the SNR. The conversion between ErrPwr and the SNR can be determined from Table 10 (intermediate values can be found by interpolation). The specified value must be written to the data field. In a few cases, several values are provided for selecting a specific mode and one of the specified values must be written to the data field. Enables the power level adjuster to correct for deviations in the signal power due to adjacent channel interference. The value is set to 1 to enable soft reset of the QAM.
ErrPwr Factory Defined Value
JitPwr Pwrlvl_correctEn QAM_Enable QAM_SoftResetEnable State SymbolCnt[9:0] SymbolKCnt
Table 10. SNR to ErrPwr Conversion
SNR(dB) 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 256 QAM 18 23 28 36 44 55 69 84 100 118 135 151 164 176 185 ErrPwr 64 QAM 16 QAM
23 28 35 44 55 68 83 101 118 137 155 171 185 198
20 26 33 41 51 64 78 95 113 131 148 163 174 184
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Receiver Description Bank 0, Group 2, Sub-Group `B' - DDC, Nyquist, AGC, and AFC Address Range Registers Table 11. Group 2, Sub-Group 'B' Read/Write Registers
Address
0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH AGC_GainSel
7
6
5
4
3
2
1
UpdateEn CorrectEn
0
Correct_ addsub Update_ addsub
Factory Defined Value - 34H DeltaTheta_in[5:0] DeltaTheta_in[13:6] Nyquist_AlphaSel Factory Defined Value - 00H AGC_ThresholdA AGC_ThresholdB
AGC_InvertOu tputB
AGC_Invert OutputA
Factory Defined Value - 22H = 16 QAM, 2BH = 64 QAM, or 35 H = 256 QAM Factory Defined Value - 26H 16 QAM, 37H 64 QAM, or 3CH 256 QAM Factory Defined Value - 52H = Signal BW ~5MHz or 3BH = Signal BW ~7MHz AFC_Cntr_stop1 AFC_Cntr_stop2 WARNING: SHOULD NOT BE PROGRAMMED BY THE USER
Table 12. Group 2, Sub-Group 'B' Read-Only Registers
Address
46H 47H 48H 49H 4AH 4BH 4C H 4DH 4EH 4FH 50H 51H 52H Factory Use Only Factory Use Only Factory Use Only DDC_DeltaTheta[3:0] DDC_DeltaTheta[11:4] Factory Use Only Factory Use Only Factory Use Only Factory Use Only Factory Use Only AGC_PowerEstimate[7:0] AGC_PowerEstimate[9:8] DDC_DeltaTheta [13:12]
7
6
5
4
3
Factory Use Only Factory Use Only
2
1
0
STEL-2176
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Receiver Description Bank 0, Group 2, Sub-Group 'B' Register Data Field Descriptions AFC_Cntr_stop1[7:0] AFC_Cntr_stop2[7:0] AGC_GainSel[3:0] AGC_InvertOutputA Set the upper limit for the first frequency offset estimate. Set the upper limit for the second frequency offset estimate. Sets the gain of the AGC. The effective gain is 1/(2GainSel). GainSel defaults to 2, and will normally range from 2 to 8. InvertOutputA is a checkbutton that inverts the polarity of the AGC's output bits (default is off). When InvertOutput is off, then a low AGC output bit means that the current power estimate is greater than the corresponding Threshold. InvertOutputB is a checkbutton that inverts the polarity of the AGC's output bits (default is off). When InvertOutput is off, then a low AGC output bit means that the current power estimate is greater than the corresponding Threshold. There are two gain amplifiers. ThresholdA sets the AGCs power threshold (0 to 2^8-1) of one amplifier. For 256-QAM, the value ranges from about 75 to 100 (default is 96), depending on the desired A/D clipping level. There are two gain amplifiers. ThresholdB sets the AGCs power threshold (0 to 2^8-1) of one amplifier. For 256-QAM, the value ranges from about 75 to 100 (default is 96), depending on the desired A/D clipping level. Correct_addsub should always be the opposite of Update_addsub. Update_addsub controls which way the NCO rotates, thereby selecting either the positive or negative passband sidelobe. This allows spectrum inversion. The hardware default value is 1, which selects the positive sidelobe (spectrum inversion off). CorrectEn should be set to 1. When set to 0, the DDC ignores the AFC's frequency correction.
AGC_InvertOutputB
AGC_PowerEstimate[9:0] AGC_ThresholdA[7:0]
AGC_ThresholdB[7:0]
Correct_addsub Update_addsub
CorrectEn DDC_DeltaTheta DeltaTheta_in[13:0]
DeltaTheta_in[13:0] sets the initial phase increment of the NCO, thereby specifying the carrier frequency, fc. DeltaTheta_in should be initialized depending on the carrier and the sampling frequencies: DeltaTheta_in = round (fc /fs *214), where fs is the sample clock frequency. Note that fs will be 25 to 30 MHz and fc will be 6 MHz or 7 MHz. E.g., for fc = 6 and fs = 25, DeltaTheta_in = 6/25 *214 = 3932 fc = (DeltaTheta_in/2 14) * f s , Factory Defined Value The specified value must be written to the data field. In a few cases, several values are provided for selecting a specific mode and one of the specified values must be written to the data field. Factory Use Only This data field is used by the factory and its function is not related to the STEL-2176 receive and transmit characteristics. Nyquist_AlphaSel[1:0] Selects the excess BW of the Nyquist matched filter: 00 -> 12% 01 -> 15% 10 -> 18% 11 -> not valid UpdateEn Should be set to 1. When set to 0, the DDC's NCO is frozen. WARNING: SHOULD This data field is used by the factory and the programmed value will affect the STELNOT BE PROGRAMMED 2176 receive and transmit characteristics. The factory programmed value should not be BY THE USER changed by the user. If inadvertently changed, the receiver must be reset. User Manual
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STEL-2176
Receiver Description Bank 0, Group 2, Sub-Group 'C' - Timing Address Range Register Table 13. Group 2, Sub-Group 'C' Read/Write Registers
Address
1C H 1DH 1EH 1FH 20H
7
6
Ratio_in[5:2]
5
4
3
2
1
0
Factory Defined Value - 14H Factory Defined Value - 3H Ratio_in[13:6] Ratio_in[21:14] Factory Defined Value - 42H
Table 14. Group 2, Sub-Group 'C' Read-Only Registers
Address
53H 54H 55H 56H 57H 58 H 59 H 5AH 5BH
7
6
5
4
3
2
1
0
Ratio_out[1:0]
Factory Use Only
Factory Use Only Factory Use Only Factory Use Only Factory Use Only Ratio_out[9:2] Ratio_out[17:10] Ratio_out[21:18] Pwrlvl_PowerEstimate[6:0] Pwrlvl_powerEstimate[10:7]
Factory Use Only
Factory Use Only
Bank 0, Group 2, Sub-Group 'C' Register Data Field Descriptions Factory Defined Value The specified value must be written to the data field. In a few cases, several values are provided for selecting a specific mode and one of the specified values must be written to the data field. This data field is used by the factory and its function is not related to the STEL-2176 receive and transmit characteristics.
Factory Use Only Pwrlvl_powerEstimate[10:0] Ratio_in[21:2] Ratio_out[21:0]
Bank 0, Group 2, Sub-Group 'D' - FFE Address Range Registers Table 15. Group 2, Sub-Group 'D' Read/Write Registers
Address
21H
7
6
5
DDenable
4
UpdateEn
3
2
1
CenterTapAddr
0
Factory Defined Value 2H = 16 QAM, 0H = 64 QAM, or 3H = 256 QAM ShiftSel_W3[1:0]
22H 23H
Factory Defined Value - 1A H =16 QAM, 1DH = 64 QAM, or 1DH = 256 QAM ShiftSel_W2[2:0] ShiftSel_W1[2:0]
24H
Factory Defined Value - 0H
ShiftSel_W5[2:0]
ShiftSel_W4[2:0]
Factory Defined Value - 0H ShiftSel_W3[2]
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Receiver Description Table 16. Group 2, Sub-Group 'D' Read-Only Registers
Address
5C H 5DH 5EH 5FH 6BH 6C H 6DH 6EH 6FH 70H 71H 72H 73H 74H 75H 76H 77H 78H 79H 7AH 7BH 7C H 7DH 7EH 7FH 80H 81H 82H 83H 84H 85H 86H 87H 88H 89H 8AH 8BH 8C H 8DH 8EH 8FH 90H 91H 92H 93H 94H 95H 96H 97H 98H 99H 9AH
7
6
5
4
3
Factory Use Only Factory Use Only Factory Use Only Factory Use Only WI0[7:0] WI0[15:8] WQ0[7:0] WQ0[15:8] WI1[7:0] WI1[15:8] WQ1[7:0] WQ1[15:8] WI2[7:0] WI2[15:8] WQ2[7:0] WQ2[15:8] WI3[7:0] WI3[15:8] WQ3[7:0] WQ3[15:8] WI4[7:0] WI4[15:8] WQ4[7:0] WQ4[15:8] WI5[7:0] WI5[15:8] WQ5[7:0] WQ5[15:8] WI6[7:0] WI6[15:8] WQ6[7:0] WQ6[15:8] WI7[7:0] WI7[15:8] WQ7[7:0] WQ7[15:8] WI8[7:0] WI8[15:8] WQ8[7:0] WQ8[15:8] WI9[7:0] WI9[15:8] WQ9[7:0] WQ9[15:8] WI10[7:0] WI10[15:8] WQ10[7:0] WQ10[15:8] WI11[7:0] WI11[15:8] WQ11[7:0] WQ11[15:8]
2
1
0
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STEL-2176
Receiver Description Bank 0, Group 2, Sub-Group 'D' Register Data Field Descriptions CenterTapAddr DDenable Defines which the taps address that will be set as the "center-tap". There are 12 taps in the FFE that can be designated as the center-tap (0 to 11). Allows the FFE to switch to Odecision-directedO (DD) mode; otherwise the FFE will remain in its "blind" equalization mode, aka CMA (constant modulus algorithm) mode. The specified value must be written to the data field. In a few cases, several values are provided for selecting a specific mode and one of the specified values must be written to the data field. This data field is used by the factory and its function is not related to the STEL2176 receive and transmit characteristics. The setting specifies the step size of the FFE, the nominal value is 2. The setting specifies the step size of the FFE, the nominal value is 2. The setting specifies the step size of the FFE, the nominal value is 2. The setting specifies the step size of the FFE, the nominal value is 2. ShiftSel_W5[2:0] sets the step size when the PLL is acquiring. Enables update of the feedforward equalizer (FFE). Current in-phase feedforward equalizer coefficients. Current quadratic feedforward equalizer coefficients.
Factory Defined Value
Factory Use Only ShiftSel_W1[2:0] ShiftSel_W2[2:0] ShiftSel_W3[2:0] ShiftSel_W4[2:0] ShiftSel_W5[2:0] UpdateEn WI0[15:0] to WI11[15:0] WQ0[15:0] to WO11[15:0]
Bank 0, Group 2, Sub-Group 'E' - FBE Address Range Registers Table 17. Group 2, Sub-Group 'E' Read/Write Registers
Address
25H 26H
7
6
Factory Defined Value - 7H
5
4
Update_En
3
2
1
0
Factory Defined Value 1H Factory Defined Value - 7FH
ShiftSel_W_DD[1:0]
Table 18. Group 2, Sub-Group 'E' Read-Only Registers
Address
9BH 9C H 9DH 9EH 9FH A0H A1H A2H A3H A4H A5H A6H A7H
7
6
WQ0[3:0]
5
4
WI0[7:0]
3
2
WI0[11:8]
1
0
WQ0[[11:4] WI1[7:0] WQ1[3:0] WQ1[[11:4] WI2[7:0] WQ2[3:0] WQ2[[11:4] WI3[7:0] WQ3[3:0] WQ3[[11:4] WI4[7:0] WI3[11:8] WI2[11:8] WI1[11:8]
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Receiver Description
A8H A9H AAH ABH ACH WQ4[3:0] WQ4[[11:4] WI5[7:0] WQ5[3:0] WQ5[[11:4] WI5[11:8] WI4[11:8]
Bank 0, Group 2, Sub-Group 'E' Register Data Field Descriptions Factory Defined Value The specified value must be written to the data field. In a few cases, several values are provided for selecting a specific mode and one of the specified values must be written to the data field. Sets the step size for the FBE when the system initially switches the equalizers to DD mode. Enables update of the feedback equalizer (FBE). Current in-phase feedback equalizer coefficients. Current quadratic feedback equalizer coefficients.
ShiftSel_W_DD Update_En WI0[11:0] to WI5[[11:0] WQ0[11:0] to WQ5[[11:0]
Bank 0, Group 2, Sub-Group 'F' - PLL Address Range Registers Table 19. Group 2, Sub-Group 'F' Read/Write Registers
Address
27H 28H 29H 2AH 2BH 2C H 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3C H 3DH 3EH 3FH
7
6
5
4
3
2
1
0
Factory Defined Value - 64H Factory Defined Value - 2A H Factory Defined Value - F4H Factory Defined Value - D6 H Factory Defined Value - 64H Factory Defined Value - 2A H Factory Defined Value - F4H Factory Defined Value - D6 H Factory Defined Value - 64H Factory Defined Value - 2A H Factory Defined Value - F4H Factory Defined Value - D6 H Factory Defined Value - 3FH FBE_ShiftSel_W_Lock FFE_ShiftSel_W_Lock Factory Defined Value - 80H Factory Defined Value - 00H Factory Defined Value - 3FH Factory Defined Value - 3H Factory Defined Value - 1FH Factory Defined Value - 1FH Factory Defined Value - 88H Factory Defined Value - 14H Factory Defined Value - 88H Factory Defined Value - 14H Factory Defined Value - 88H Factory Defined Value - 14H
FFE_ShiftSel_W_DD
UpdateEn Factory Defined Value - 7H
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STEL-2176
Receiver Description Table 20. Group 2, Sub-Group 'F' Read-Only Registers
Address
60H to 68H 69H 6AH
7
6
5
4
3
Factory Use Only [7:0] DeltaPhase[15:8]
2
1
0
Bank 0, Group 2, Sub-Group 'F' Register Data Field Descriptions DeltaPhase[15:0] Factory Defined Value Specifies the initial value for the PLL's phase increment. The specified value must be written to the data field. In a few cases, several values are provided for selecting a specific mode and one of the specified values must be written to the data field. This data field is used by the factory and its function is not related to the STEL2176 receive and transmit characteristics. Sets the step size of the FBE when the system has "locked" (steady-state operation). Sets the step size of the FFE when the system initially switches the equalizers to DD mode Sets the step size of the FFE when the system has "locked" (steady-state operation). UpdateEn should be high; if UpdateEn is low, the PLL is disabled.
Factory Use Only FBE_ShiftSel_W_Lock[1:0] FFE_ShiftSel_W_DD[2:0] FFE_ShiftSel_W_Lock[2:0] UpdateEn
Bank 1 - FEC Registers (Group 3) The QAM Demodulator Registers Universal Registers are divided into 7 sub-groups of registers. Each subSub-Group A B C D E F G Name Viterbi and De-Mapper De-Randomizer De-Interleaver MPEG Frame Sync Frame Sync Output Clk Reed-Solomon Decoder
group can have a Read/Write set of registers which are used for control purposes, a Read-only set which are used for monitoring purposes, or a combination of both types of registers. The sub-groups are:
Read/Write Register Addresses 00H Not Used 45H to 48H 4BH to 4EH 53H to 57H 66H to 6AH 70H ,71 H, and 74H Read-only Register Addresses Not Used 41H 43H to 44H and 49H to 4AH 4F H to 52H 58H to 65H Not Used 72H to 73H
Bank 1, Group 3, Sub-Group 'A' - Viterbi and De-Mapper Registers Table 21. Group 3, Sub-Group 'A' Read/Write Registers
Address
00H
7
DVB & IEEE 802.14 map
6
5
4
3
2
1
0
Factory Defined Value - 3H
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Receiver Description Bank 1, Group 3, Sub-Group 'A' Register Data Field Descriptions DVB & IEEE 802.14 map Factory Defined Value Set the value to 1 to select 256 QAM DVB & IEEE 802.14 demapper, 0 selects the DAVIC 256 QAM demapper. The specified value must be written to the data field. In a few cases, several values are provided for selecting a specific mode and one of the specified values must be written to the data field.
Bank 1, Group 3, Sub-Group 'B' - De-Randomizer Registers Table 22. Group 3, Sub-Group 'B' Read-Only Registers
Address
41H
7
Not Used
6
5
4
3
DataOut[6:0]
2
1
0
Bank 1, Group 3, Sub-Group 'B' Register Data Field Descriptions DataOut
Bank 1, Group 3, Sub-Group 'C' - De-Interleaver Registers Table 23. Group 3, Sub-Group 'C' Read/Write Registers
Address
45H 46H 47H 48H
7
6
5
4
Not used Not used I_test
3
2
1
ShadowMode
0
Level2 TestMode
Not used
J_test
Table 24. Group 3, Sub-Group 'C' Read-Only Registers
Address
43H 44H 49H 4AH
7
6
5
4
3
I_test J_test SRAM_addr[15:8] SRAM_addr[7:0]
2
1
0
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STEL-2176
Receiver Description Bank 1, Group 3, Sub-Group 'C' Register Data Field Descriptions I_test (Read/Write) I_test (Read-Only) J_test (Read/Write) J_test (Read-Only) Level2 The I value used during test mode. Read register that permits looking at I value when the interleaver is running during test. The J value used during test mode. Read register that permits looking at J value when the interleaver is running during test. There are two distinct operating modes of interleaving for Annex B. If Level2 is 1, the depth of interleaving is variable and depends on a control word from Frame Sync. If Level2 is 0 (level 1), interleaving is always 128 X 1; the control word does not matter. There is 8 Kbytes of internal memory for the interleaver. In normal operation, the interleaver first fills up its internal memory, then uses external memory. If Shadow mode is 1, internal memory is bypassed. The address is used by the interleaver to access the SRAM. For Annex A, 256QAM requires external SRAM. The Interleaving type is set elsewhere by selecting QAM and Annex type. Setting this register to 1, enables use of the I and J values stored in the I_test and J_test Read/Write registers.
ShadowMode
SRAM_addr[15:0] TestMode
Bank 1, Group 3, Sub-Group 'D' - MPEG FrameSync Registers Table 25. Group 3, Sub-Group 'D' Read/Write Registers
Address
4BH 4C H 4DH 4EH
7
6
5
4
3
2
1
0
HIT MISS SyncSymbol Not used
OP_ERR
Table 26. Group 3, Sub-Group 'D' Read-Only Registers
Address
4FH 50H 51H 52H
7
6
5
4
3
Factory Use Only Factory Use Only Factory Use Only Factory Use Only
2
1
0
STEL-2176
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User Manual
Receiver Description Bank 1, Group 3, Sub-Group 'D' Register Data Field Descriptions Factory Use Only HIT MISS OP_ERR SyncSymbol This data field is used by the factory and its function is not related to the STEL2176 receive and transmit characteristics. The number of Syncs that must be detected before data is output. The number of misses before the MPEG Frame Sync state machine goes into idle. Setting the value to 1 enables flagging of data errors via the checksum in the Frame Sync byte. Used in Annex A only to input an arbitrary MPEG FRAME sync symbol; normally 47H.
Bank 1, Group 3, Sub-Group 'E' - FrameSync Registers Table 27. Group 3, Sub-Group 'E' Read/Write Registers
Address
53H 54H 55H 56H 57H
7
6
5
4
3
TRACK[7:0] HIT[7:0] MISS[7:0] SyncSymbol[7:0]
2
1
ErrorTolEn
0
NoMissMode
ErrorTolerance[5:0]
Table 28. Group 3, Sub-Group 'E' Read-Only Registers
Address
58H to 65H
7
6
5
4
3
Factory Use Only
2
1
0
Bank 1, Group 3, Sub-Group 'D' Register Data Field Descriptions Factory Use Only NoMissMode ErrorTolEn ErrorTolerance TRACK HIT MISS SyncSymbol This data field is used by the factory and its function is not related to the STEL2176 receive and transmit characteristics. If NoMissMode is 1, then once Frame Sync is acquired the state machine will never go to the idle mode, even if all data is bad. If ErrorTolEn is 1, then all bits in the Frame Sync sequence must match the expected pattern. This is for Annex B only. Sets the number of bits that can be wrong in the Frame Sync sequence and have the sequence considered valid. The number of frames the Frame Sync state machine must detect before telling the Viterbi that data should be realigned. This is for Annex B only. The number of Syncs that must be detected before data is output. The number of misses before the Frame Sync state machine goes into idle. Used in Annex A only to input an arbitrary FRAME sync symbol; normally 47H.
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STEL-2176
Receiver Description Bank 1, Group 3, Sub-Group 'F' - OutputClk Registers Table 29. Group 3, Sub-Group 'F' Read/Write Registers
Address
66H 67H 68H 69H 6AH
7
6
5
4
3
2
1
0
Nominal_value[7:0] Nominal_Value[15:8] Not Used Not Used Nominal_Value[19:16] ByPass LSB_First Mode Scale[3:0] Serial Mode
Bank 1, Group 3, Sub-Group 'F' Register Data Field Descriptions ByPass Mode LSB_First Nominal_Value[19:0] Setting to 0, enables output clock block to eliminate gaps between MPEG frames. set The 20-bit value is programmed according to the Annex and QAM type, as shown below. It controls how fast the output clock is operating by setting the ratio of the high speed clock to the output clock. Annex A 16-QAM 64-QAM 256-QAM Scale Controls the amount of jitter in the output clock. If Scale is set to low, acquisition of the input data will be slower (i.e., locking onto it will take longer) but the clock will be smoother. If Serial Mode is 1, the data is serial. Annex B STEL Use Only
Serial Mode
Bank 1, Group 3, Sub-Group 'G' - Reed-Solomon Decoder Registers Table 30. Group 3, Sub-Group 'G' Read/Write Registers
Address
70H 71H 74H
7
6
Not Used
5
4
3
2
1
0
Factory Defined Value - CC H = Annex A:, 80 H = Annex B: OutputDataRate Not Used
CLR_ERR
Table 31. Group 3, Sub-Group 'G' Read-Only Registers
Address
72H 73H
7
6
5
4
3
Error_cnt[7:0] Error_cnt[15:8]
2
1
0
STEL-2176
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User Manual
Receiver Description Bank 1, Group 3, Sub-Group 'G' Register Data Field Descriptions Factory Defined Value The specified value must be written to the data field. In a few cases, several values are provided for selecting a specific mode and one of the specified values must be written to the data field. Clears the Error_cnt register Error_cnt[7:0] is byte 0 of the number of errors found in a block and Error_cnt[15:8] is byte 1 of the number of errors found in a block.
The value to be written to the OutputDataRate data field is dependent on the value of
CLR_ERR Error_cnt[15:0] OutputDataRate
Register FEH[3:0]. When Register FE H[3:0] is: 0H 1H 2H 4H 5H 6H 8H 9H AH OutputDataRate[4:0] should be set to: 10H Not Valid 10H 0AH 08H 0AH 08H 07H Not Valid
with one byte per symbol.
TIMING
The basic input to the receiver is an analog input; basic outputs consist of data (serial or parallel), an output clock and a frame sync. These outputs are shown in the four timing diagrams that follow. There are four output modes depending on whether there are gaps between frames and depending on whether the data output is parallel (8 bit) or serial. The addition of the Read-Solomon checksum creates gaps in the transmission of the MPEG-2 frame. But the STEL-2176 provides the option of spreading the gap over a frame so there appears to be no gap. For gap or no-gap mode, data may be parallel or serial. The four modes are as follows:
NO GAP, SERIAL MODE
This is similar to the above. Here the frame length is 8EX 188 bits, and the Output Clock is for a bit period rather than a byte period.
GAPS, PARALLEL MODE
In this mode there are two differences: The Output Clock 8Enanoseconds. is now approximately
The Output Clock goes for 188 bytes, then the data and clock stop until Frame-Sync/ is asserted again.
GAPS, SERIAL MODE
This mode is the same as above, but here the bytes are serialized. There are 8 X 188 clocks and 8 X 188 bits per Frame-Sync/.
NO GAP, PARALLEL MODE
Here Frame-Sync/ indicates the first byte of an MPEG-2 frame, and Output Clock is approximately 50% of the byte period. There are 188 bytes in a frame User Manual
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STEL-2176
Receiver Description
DOWNSTREAM OUTPUT TIMING (SERIAL DATA OUTPUT)
Case 1: No Gaps between MPEG-2 Frames.
Frame-Sync/
Data (7..0)
MPEG-2 Sync
Output Clock ~50% of Byte's Period
TPG 53298.c-7/28/97
Figure 19.
DOWNSTREAM OUTPUT TIMING (SERIAL OUTPUT)
Case 1: No Gaps between MPEG-2 Frames.
Frame-Sync/ D ata, MSB, or LSB first Output Clock
~50% of bits's Period
TPG 53300.c-7/28/97
Figure 20. STEL-2176
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User Manual
Receiver Description
DOWNSTREAM OUTPUT TIMING (PARALLEL DATA OUTPUT)
Case 1: Gaps between MPEG-2 Frames. 188 Bytes, and 204 Clocks Frame-Sync/
Data (7..0)
MPEG-2 Sync
Output Clock
~8 n.sec After 188 clocks and bytes, starting from the Frame Sync, The output clock will stay `low' till next Frame Sync.
TPG 53299.c-7/28/97
Figure 21.
DOWNSTREAM OUTPUT TIMING (SERIAL DATA OUTPUT)
Case 1: No Gaps between MPEG-2 Frames.
Frame -Sync/ Data, MSB, or L SB first Output Clock
~8 n.sec After 8*204 clocks and 8*204 bITS, starting fro m the Frame Sync, The output clock will stay `low' till next Ftame Sync.
TPG 53297.c-7 /28/97
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STEL-2176
Receiver Description
Figure 22.
DE-INTERLEAVER EXTERNAL SRAM TIMING
Internal clock (RES_CLK)
SRAM ADDRESS
SRAMOEb_
15 nsec min.
15 nsec min.
15 nsec min.
SRAMWEb_
SRAMDATA
15 nsec max
0 nsec min.
15 nsec min.
15 nsec min.
15 nsec min.
WCP 53888.C-12/6/97
Figure 23.
STEL-2176
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User Manual
Transmitter Description
TRANSMITTER
INTRODUCTION
The STEL-21761 contains a highly integrated, maximally flexible, burst transmitter targeted to the cable modem market. It receives serial data, randomizes the data, performs FEC and differential encoding, maps the data to a constellation before modulation, and outputs an analog RF signal. The STEL-2176 is the latest in a series of modulator chips that comprise the STEL-1103 through STEL-1109 modulators. Several key components (e.g., a 64-bit FIR and a clock multiplier) have been incorporated in the STEL-2176 and the enhancements have resulted in significant improvements to the chipOs performance. The STEL-2176 is capable of operating at data rates of up to 10 Mbps in BPSK mode, 20 Mbps in QPSK mode, and 40 Mbps in 16QAM mode. It operates at clock frequencies of up to 165 MHz, which allows its internal, 10-bit Digital-to-Analog Converter (DAC) to generate RF carrier frequencies of 5 to 65 MHz. The STEL-2176 also uses digital FIR filtering to optimally shape the spectrum of the modulating data prior to modulation. This optimizes the spectrum of the modulated signal, and minimizes the analog filtering required after the modulator. The filters are designed to have a symmetrical (mirror image) polynomial transfer function, thereby making the phase response of the filter linear. This also eliminates the inter-symbol interference that results from group delay distortion. In this way, it is possible to change the carrier frequency over a wide frequency range without having to change filters, thus providing the ability to operate a single system in many channels. The STEL-2176 can operate with very short gaps between transmitted bursts to increase the efficiency of Time Division Multiple Access (TDMA) systems. The STEL-2176 operates properly even when the interburst gap is less than four (4) symbols (half the length of the FIR filter response). In this case the
1
postcursor of the previous burst overlaps and is superimposed on the precursor of the following burst. Signal level scaling is provided after the FIR filter to allow the STEL-2176Os maximum arithmetic dynamic range to be utilized. Signal levels can be changed over a wide range depending on how the device is programmed. In addition, the STEL-2176 is designed to operate from a 3.3 Vdc power supply and the chip can be interfaced with logic that operates at 5 Vdc.
FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS
The STEL-2176 is comprised of the Data Path (see page 39) and Control Unit (see page 52) sections shown in Figure 24. The Data Path is comprised of a Bit Sync Block, Bit Encoder Block (i.e.,Ethe Scrambler, Reed-Solomon Encoder, and two Multiplexers shown in Figure 25), Symbol Mapper Block (i.e., the Bit Mapper, Differential Encoder, and Symbol Mapper are shown in Figure 28), two channels (one for I and one for Q), a Combiner, and a 10-bit DAC. Each channel consists of a Nyquist Filter, Interpolation Filter, and Modulator. The Control Unit is comprised of a Bus Interface Unit (BIU), Clock Generator, and NCO. Table 32 summarizes the main features of the circuits described by the remaining paragraphs of this section.
DATA PATH DESCRIPTION
Bit SYNC Block The Bit Sync Block has two functions: latching input data, and synchronizing the STEL-2176 TXBITCLK and symbol counters to the user data.
The STEL-2176 utilizes advanced signal processing techniques which are covered by U.S. Patent Number 5,412,352.
PRODUCT INFORMATION
39
STEL-2176
Transmitter Description
Table 32. Transmit Features
Feature Carrier frequency: Symbol rate: FIR filter tap coefficients: Modulation: 16QAM constellation: I and Q modulator signs / Spectral Inversion Reed-Solomon Encoder: Characteristic 5 to 65 MHz (maximum of approximately 40% of master clock) From Master clock divided by 16 down to Master clock divided by 16384 (in steps of 4) yielding a maximum symbol rate of 10 Msps with a 160 MHz clock. 64 programmable taps (10 bits each), symmetric response BPSK, QPSK, or 16QAM Eight selectable bit-to-symbol mappings Five selectable symbol-to-constellation mappings Signs of I and Q plus the mapping to Sine and Cosine carriers is programmable. Selectable on/off Two selectable generator polynomials Block length shortened any amount Error correction capability T = 1 to 10 Selectable on/off Self-synchronizing or frame synchronized (sidestream) Location before or after RS Encoder Programmable generator polynomial Programmable length up to 224 - 1 Programmable initial seed Selectable on/off
Scrambler:
Differential Encoder:
TXDIFFEN TXTCLK TXTSDATA BIT Sync Block I[1:0], Q[1:0] TXDATAENI TXRDSLEN TXSCRMEN VDDA VDD5 VDD TXRSTB Master Clock Generator BIT Encoder Block 4
DATA PATH
I[1:0] Symbol Mapper Block 2 Q[1:0] 2 Nyquist Filter Nyquist Filter Interpolating Filter Modulator Interpolating Filter TXDATAENO 10-Bit DAC DACOUTP DACOUTN
TXCKSUM
SAMPLS MASTER CLOCK (CLK) TXBITCLK TXSYMPLS TXACLK
TXCLKEN TXCLK
COS 2FT TXNCOLD TXFCWSEL1-0 DATA7-0 ADDR5-0 DSB WRB CS Bus Interface Unit (Group 2 Registers) Numerically Controlled Oscillator SIN 2FT
WCP 53806.c-12/7/97
Figure 24. STEL-2176 Transmitter Block Diagram STEL-2176
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User Manual
Transmitter Description
Table 33. Data Latching Options
Data Source TXTSDATA TXTSDATA PN Code 10, 3 PN Code 23, 18 Latched By TXBITCLK TXTCLK TXBITCLK TXBITCLK Register 2C Bit 7 0 1 0 0 Register 2D Bits 1,0 X,0 X,0 0,1 1,1 Mode Name Master Mode Slave Mode Test Mode Test Mode
Latching Input Data Latching of input data is accomplished in one of three modes: * * * Externally supplied TXTSDATA is latched by the internal TXBITCLK (Master mode). Externally supplied TXTSDATA is latched by an externally provided TXTCLK (Slave mode). Internally generated PN code data is latched by the internal TXBITCLK (Test mode).
TXCLKEN goes low. For applications that will not allow TXCLKEN to cycle low between bursts, some system level precautions should be observed to maintain synchronization of user data to the STEL-2176 TXBITCLK. Once triggered, the sync circuit re-starts the TXBITCLK and TXSYMPLS counters. The TXBITCLK output starts high, and TXSYMPLS resets to the start of a symbol. There is a delay equal to about three cycles of the master clock from the rising edge of the TXTCLK input before this re-start occurs. During this brief delay period, the TXBITCLK and TXSYMPLS counters are still free running and may or may not have transitions. In master mode, the rising edge of TXTCLK normally marks the transition of the first user data bit (which will be latched in by the next falling edge of TXBITCLK). In slave mode, the first user data bit must already be valid at this first rising edge of TXTCLK. Bit Encoder Block The Bit Encoder Block consists of a Scrambler, a Reed-Solomon Encoder, and data path controls (multiplexers), as shown in Figure 25. Data Path Control (Multiplexers) The STEL-2176 provides a great deal of flexibility and control over the routing of data through or around the encoding functions. With appropriate register selections, data can be routed around (bypass) both encoders, through either one and around the other, through the scrambler then the RS Encoder, or through the RS Encoder and then the scrambler. Control over the bypassing can be set for software control or external (user) input signal control. Generally, if an encoding function will be left either on or off continuously, then software control is appropriate. If the function must be turned on and off dynamically (typically in order to send the preamble Oin the clearO i.e. unencoded), then external (user) input control is required. If the ReedSolomon encoder will not be used at all, then a separate
See Table 33 for register settings to implement each mode. TXBITCLK latches data on its falling edge. TXTCLK latches data on its rising edge. Whenever the TXCLKEN input is low, the TXBITCLK output will stop. There is also an auxiliary continuous clock (TXACLK) output which is discussed later in the clock generator section. The TXACLK output is primarily for use in master mode where users may need a clock to run control circuits during the time between bursts. When using slave mode, the data that is latched by the rising edge of TXTCLK is re-latched internally by the next falling edge of TXBITCLK which re-synchronizes the data to the internal master clock. Synchronizing TXBITCLK / TXSYMPLS The synchronization circuit aligns the STEL-2176 TXBITCLK and its TXSYMPLS counter circuits to the beginning of the first user data symbol. The circuit has two parts, an arming circuit and a trigger circuit. Once armed, the first rising edge on the TXTCLK input will activate (trigger) the synchronization process. The circuit can be armed in two ways; taking TXCLKEN from low to high, or toggling Block 2 Register 2EH bit 0 from low to high to low again. In a normal burst mode application, the circuit is automatically re-armed between bursts because
User Manual
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STEL-2176
Transmitter Description
Input Multiplexer
Output Multiplexer
bypass option can be activated to remove an 8-bit delay register from the data path that is required if the possibility of turning on the encoder exists. Each of the external (user) input control pins (if enabled) turns on the encoding function when high and bypasses the function when low. The TXDATAENI input signal determines whether or not data will advance (shift through) the encoding blocks. The presence of a high on the TXDATAENI input when the TXBITCLK output goes low allows the circuits to advance data through them. The TXDATAENI signal is delayed internally to allow the rising edge of TXDATAENI to coincide with the first rising edge of TXTCLK.
TXSCRMEN
SERIAL DATA TXDATAEN
Scrambler
ENCODED SERIAL DATA
Reed-Solomon Encoder
TXRDSLEN S-RS
CHKSUM SIGNAL
WCP 53808.c-12/5/97
Figure 25. Bit Encoder Functional Diagram See Table 34 for a summary of register settings required to achieve the various data path possibilities.
Table 34. BIT Encoding Data Path Options
Data Path Data stopped (continuously) Data path on (continuously) Data path enabled by pin 109 Scrambler off (continuously) Scrambler on (continuously) Scrambler enabled by pin 118 RS Encode off (continuously) RS Encode on (continuously) RS Encode enabled by pin 117 Scrambler then RS Encoder RS Encoder then Scrambler Bypass RS Encoder Register 36 Bits 6,5 X,X X,X X,X X,X X,X X,X 1,X 1,X 1,X 1,1 1,0 0,X Register 38 Bits 7-2 01 XXEXX 11 XXEXX X0 XXEXX XXEXX 01 XXEXX 11 XXEXX X0 XX 01 XX XXE11 XX XXEX0 XX XXEXXEXX XXEXXEXX XXEXXEXX
Scrambler The scrambler can be used to randomize the serial data in order to avoid a strong spectral component that might otherwise arise from the occurrence of repeating patterns in the input data. The Scrambler (Figure 26) uses a Pseudo-Random (PN) generator to
generate a PN code pattern. All 24 registers are presettable and any combination of the registers can be connected (tapped) to form any polynomial of up to 24 bits. The scrambler may be either frame synchronized or self synchronized. Table 35 shows the registers involved.
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Transmitter Description
24-bit Mask Reg 24-bit INIT Reg 24-bit Shift Reg
1 1
2 2
3 3
22 23 22 23
24 24
1
2
3
22
23
24
(enabled). Internal delays on the TXSCRMEN control signal input allow for a rising edge to occur coincident with the rising edge of TXBITCLK that precedes the latching of the first data bit to be scrambled. The Mask, Init, and SSync fields can be programmed for different scrambler configurations. For example, the DAVIC Scrambler configuration shown in Figure 27 can be implemented by programming the Mask, Init, and SSync fields with the values indicated by Table 36.
1 0 2 0 3 1 4 0 5 1 6 0 7 1 8 0 9 0 10 0 11 0 12 0 13 0 14 0 15
XOR
TXSCRMEN SERIAL INPUT
AND
SERIAL OUTPUT
XOR
1
SELF SYNC MUX
FRAME SYNC
SSYNC
EX-OR
WCP 53809.c-12/2/97
Figure 26. Scrambler Block Diagram
AND
The value in the INIT registers is loaded into the scrambler shift registers whenever the scrambler is at disabled. The scrambler will scramble data one bit a time at each falling edge of TXBITCLK that occurs while both the scrambler and TXDATAENI are active
EX-OR
Randomized Data
Enable
Clear Data Input
WCP 52984.c-4/26/97
Figure 27. DAVIC Scrambler
Table 35. Scrambler Parameters
Parameter Generator Polynomial (Mask Reg) Seed (INIT Reg) Scrambler Type Scrambler Type Characteristic p(x) = c24x 24 + c23x 23 + E + c1 x + 1 where ci is a binary value (0, 1) Any 24-bit binary value, s 24-1 Frame synchronized (sidestream) Self-synchronized Register 35 Bit 7 to Bit 0 c24 to c17 Register 32 Bit 7 to Bit 0 s24 to s17 Register 36 Bit 4 Set to zero Register 36 Bit 4 Set to one Block 2 Register Setting Register 34 Register 33 Bit 7 to Bit 0 Bit 7 to Bit 0 c16 to c9 c8 to c1 Register 31 Bit 7 to Bit 0 s16 to s9 Register 30 Bit 7 to Bit 0 s8 to s1
Table 36. Sample Scramble Register Values
Parameter Generator Polynomial (Mask Reg) Seed (INIT Reg) Scrambler Type Characteristic p(x) = x 15 + x 14 + 1 Register 35 Bit 7 to Bit 0 0000E0000 Register 32 Bit 7 to Bit 0 0000E0000 Register 36 Bit 4 Set to zero Block 2 Register Setting Register 34 Register 33 Bit 7 to Bit 0 Bit 7 to Bit 0 0110E0000 0000E0000 Register 31 Bit 7 to Bit 0 0000E0000 Register 30 Bit 7 to Bit 0 1010 1001
0000A9 H Frame synchronized (sidestream)
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STEL-2176
Transmitter Description
Reed-Solomon Encoder The STEL-2176 uses a standard Reed-Solomon (RS) Encoder for error correction encoding of the serial data stream. The error correction encoding uses GF (256) and can be programmed for an error correction capability of 1 to 10, a block length of 3 to 255, and one of two primitive polynomials using the data fields listed in Table 37 When TXDATAENI is high and the RS Encoder is enabled, the serial data stream both passes straight through the RS Encoder and also into encoding circuitry. The encoding circuitry computes a checksum that is 2T bytes long for every K bytes of input data. After the last bit of each block of K bytes of input data,
the RS Encoder inserts its checksum (2T bytes of data) into the data path. There is no adverse effect to letting TXTCLK or TXTSDATA continue to run during the checksum; the data input will be ignored. TXCKSUM will be asserted high to indicate that the checksum bytes are being inserted into the data stream and will be lowered at the end of the checksum data insertion. The width of the TXCKSUM pulse is 2T bytes. The STEL-2176 registers include two bits for determining the bit order for data into and checksum out of the RS Encoder circuitry. Set these to match the ReedSolomon decoding circuitry along with the other parameters. .
Table 37. Reed-Solomon Encoder Parameters
Field Name PP Block 2 Register 36H (bit 7) 0 p(x) = x8 + x 4 + x 3 + x 2 + 1 1 p(x) = x8 + x 7 + x 2 + x + 1 T K LDLSBF TRLSBF Notes: GF (256). Code generator polynomial 1 is used when PP=1: 36H (bits 3-0) 37H (bits 7-0) 39H (bit 4) 39H (bit 5) 4-bit field for setting Error Correction Capability. Programmable over the range of 1 to 10. 8-bit field for setting User Data Packet Length (K) in bytes. Programmable over the range of 1 to (255 - 2T). [ Net block length, N = K + 2T ] Determines whether the first bit of the serial input is to be the MSB (bit 4 = 0) or LSB (bit 4 = 1) of the byte applied to the RS Encoder. Determines whether the MSB (bit 5 = 0) or LSB (bit 5 = 1) of the RS Encoder checksum byte is to be the first bit of the serial output data. Description 1-bit field for selecting Primitive Polynomial:
G(x) = G(x) =
119 + 2T i =120 2T -1 i=0
(x - ) = 02H
i i
Code generator polynomial 2 is used when PP=0.
(x - ) =
02H
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Transmitter Description
Symbol Mapper Block The Symbol Mapper Block (Figure 28) maps the serial data bits output by the Bit Encoder Block to symbols, differentially encodes the symbols, and (in 16QAM) maps the symbols to one of five constellations. The Symbol Mapper Block functions are modulation dependent. The modulation mode also defines the number of bits per symbol. The Symbol Mapper Block outputs 2 bits for each symbol to each of the two Nyquist (FIR) Filters.
I[1:0]** Q[1:0]** Bit Mapper 4 Differential Encoder 4 Symbol Mapper I[1:0]* Q[1:0]* 2 I[1:0]
Bit Mapper The Bit Mapper receives serial data and maps the serial data bits to output symbol bits (I1**, I0**, Q 1**, and Q0**). There are four output bits per symbol even in BPSK and QPSK modes. In BPSK, all bits are set equal to each other. In QPSK, each input symbol bit drives a pair of output bits. The four symbol bits are routed to the Differential Encoder in parallel. For BPSK modulation, each bit (symbol = b 0 ) of the input serial data stream is mapped directly to I1**, Q1** , I0**, and Q0 * * (i.e., I 1** = I0 * * = Q1 **= Q0 **= b0 ). Thus, bit mapping has no affect on the respective value of the symbolOs four bits, as shown in Table 38. For QPSK modulation, each pair of bits (a dibit) forms a symbol (b 0 b1 ). The QPSK dibit is mapped so that I1**E=EI0** and Q1** = Q0**, as shown in Table 38. For 16QAM, every four bits (a nibble) forms a symbol (b0b 1b 2b 3). The 16QAM nibble is mapped to I1**, Q 1** , I0**, and Q0**, as shown in Table 38.
ENCODED SERIAL DATA 1 TXDIFFEN 1
Q[1:0] 2
WCP 53810.c-12/2/97
Figure 28. Mapping Block Functional Diagram
Table 38. Bit Mapping Options
Bit-To-Symbol Mapping b1 b2 b0 Mode ** ** ** ** BPSK I1 Q1 I0 Q0 N/A N/A QPSK I1 ** I0** Q1 ** Q0** N/A QPSK Q1 ** Q0** I1 ** I0** N/A 16QAM I1 ** I0 ** Q1 ** ** ** 16QAM Q1 Q0 I1 ** ** ** 16QAM I0 I1 Q0 ** ** ** 16QAM Q0 Q1 I0 ** ** ** 16QAM I1 Q1 I0 ** ** ** 16QAM Q1 I1 Q0 ** ** ** 16QAM I0 Q0 I1 ** ** ** 16QAM Q0 I0 Q1 ** Note: b0 is the first serial data bit to arrive at the Bit Mapper b3 N/A N/A N/A Q0 ** I0 ** Q1 ** I1 ** Q0 ** I0 ** Q1 ** I1 ** Bit Mapping Mod Mode Register 2D Register 2C bits bits 6-4 3,2 XXX XX0 XX1 000 001 010 011 100 101 110 111 1X 00 00 01 01 01 01 01 01 01 01
Differential Encoder The Differential Encoder encodes the bits (i.e., I1**, I0** , Q1** , and Q0 * * ) of each symbol received from the Bit Mapper to determine the output bit values (i.e., I1*, Q1*, I0*, and Q0*), which are routed to the Symbol Mapper. The differential encoder can be either enabled or bypassed under the control of either a register bit or a user supplied control signal (TXDIFFEN). The selection between user input pin control or register control is made in another register bit, as shown in Table 39.
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STEL-2176
Transmitter Description
Table 39. Differential Encoder Control
Level/Value Encoding off (continuously) Encoding on (continuously) Encoding enabled by pin 116 high - enable the Differential Encoder low - disable the Differential Encoder Register 38 Bits 1,0 0,1 1,1 X,0
180 degree phase change if the output is high and 0Edegrees if the output is low.
QPSK
In QPSK mode, the next output dibit is found by XORing the input dibit with the current output dibit. Table 40 shows the results of the differential encoding performed for QPSK modulation and the resulting phase shift. In the table, I = I1 = I0 and Q = Q1= Q0.
16QAM
For any modulation mode, if differential encoding is disabled then: I1*Q1*I0*Q0*E=E I1**I0**Q1** Q0** If differential encoding is enabled, then the results are described below for each modulation type.
BPSK
In 16QAM mode, the differential encoding algorithm is the same as in QPSK. Only the two MSBOs, I1** and Q1** are encoded. The output bits I 0* and Q0* are set equal to the inputs bits I0** and Q0** .
In BPSK mode, the next output bit is found by XORing the input bit with the current output bit. The result is a Table 40. QPSK Differential Encoding and Phase Shift
Current Input (IQ) 00 Current Output (IQ) 00 01 10 11 01 00 01 10 11 10 00 01 10 11 11 00 01 10 11 Next Output (IQ) 00 01 10 11 01 11 00 10 10 00 11 01 11 10 01 00 Phase Shift (degrees) 0 -90 (CW) 90 (CCW) 180 -90 (CW) 180 0 90 (CCW) 90 (CCW) 0 180 90 (CCW) 180 90 (CCW) -90 (CW) 0
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Transmitter Description
Symbol Mapper The Symbol Mapper receives I1*, Q1*, I 0*, Q0 * of each symbol. Based on the signal modulation and the symbol mapping selection, the Symbol Mapper block maps the symbol to a constellation data point (I1,Q1,I0,Q 0). The Symbol Mapping field (bits 7-5 of Block 2 Register 2EH) will map the four input bits to a new value, as indicated in Table 41.
BPSK and QPSK
Mapping field (bits 7-5 of Block 2 Register 2EH) to select the type of symbol mapping. If the MSB of the Symbol Mapping field is set to 0, the mapping will be bypassed and I1Q 1I0Q0 = I1 * Q 1*I0*Q0*. The resulting constellation (Figure 31) is the natural constellation for the STEL-2176. If the MSB of the Symbol Mapping field is set to 1, bits 6-5 can select any of four possible types of symbol mapping (Gray, DAVIC, Left, or Right), as indicated by Table 41. Table 42 summarizes the symbol mapping and the resulting constellations are shown in Figure 31 and Figure 32. In these figures, I1Q1 are indicated by large, bold font (00, 01, 10, a n d 11) and I0Q0 by the smaller font (00, 01, 10, and 11).
For BPSK and QPSK, the settings of the symbol to constellation mapping bits is ignored. The constellations for BPSK (Figure 29) and QPSK (Figure 30) are shown below. I1Q1 values are indicated by large, bold font (00 and 11) and I 0Q0 values by the smaller font (00 and 11).
16QAM
For 16QAM modulation, the Symbol Mapper maps each input symbol to one of the 16QAM constellations. The specific constellation is programmed by the Symbol
Q
11
3
Q
01
3
11
11
1 -3 -1 1 3
01
1
11
-1 1 3
I
-1
-3
I
-1
00
00
-3
00
-3
10
10
00
WCP 52999.c-10/29/97
WCP 52986.c-10/29/97
Figure 29. BPSK Constellation
Figure 30. QPSK Constellation
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STEL-2176
Transmitter Description
Q
10 00 10 00
Table 41. Symbol Mapping Selections
Mapping Selection Natural Gray DAVIC
01
1 3
Register 2E Bits 7-5 0XX 100 101 110 111
10
11
-3
00
01
-1 1
Left Right
11
I
10 00 10 00
11
11 01 11
01
01
WCP 52987.c-10/29/97
Figure 31. Natural Mapping Constellation Table 42. Symbol Mapping
Input Code Natural Mapping (Bypass) I 1 * Q1* I0 * Q0 * 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Output Code I 1 Q1 I0 Q0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Gray I 1 * Q1* I0 * Q0 * 0011 0010 0001 0000 0110 0111 0100 0101 1001 1000 1011 1010 1100 1101 1110 1111
DAVIC I 1 * Q1* I0 * Q0 * 0011 0001 0010 0000 0110 0111 0100 0101 1001 1000 1011 1010 1100 1110 1101 1111
Left I 1 * Q1* I0 * Q0 * 0011 0010 0001 0000 0101 0111 0100 0110 1010 1000 1011 1001 1100 1101 1110 1111
Right I 1 * Q1* I0 * Q0 * 0011 0001 0010 0000 1010 1011 1000 1001 0101 0100 0111 0110 1100 1110 1101 1111
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User Manual
Transmitter Description
Q
11 01 01 11
Q
11 01 10 11
01
10
-3
11
00
-1 1
10
10
00
00
1 -1
00
10
-3
1
3
00
1
3
01
I
10 00 00 10
I
01 00 00 10
00
11 01 01
10
11
WCP 52988.c-10/29/97
11
11 10 01
10
11
WCP 52990.c-4/26/97
Figure 32. Gray Coded Constellation
Q
11 10 01 11
Figure 34. DAVIC Coded Constellation
Q
11 01 10 11
10
01
-3
00
00
-1 1
01
3
00
00
1 -1
00
1
10
10
I
10 00 00 01
-3
00
1
3
01
I
01 00 00 10
11
11 01 10
01
11
WCP 52989.c-4/26/97
11
11 10 01
10
11
WCP 52991.c-4/26/97
Figure 33. Left Coded Constellation
Figure 35. Right Coded Constellation
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STEL-2176
Transmitter Description
Nyquist FIR Filter The finite impulse response (FIR) filters are used to shape each transmitted symbol pulse by filtering the pulse to minimize the sidelobes of its spectrum. The Symbol Mapper Block outputs the I1I0 data to a pair of I-channel FIR filters and the Q1 Q 0 data to a pair of Q-channel FIR filters. Figure 36 shows the filter block diagram for a channel pair (I or Q). The FIR filter can be bypassed altogether or, in BPSK or QPSK modes, individual channels can be turned on and off which changes the effective filter gain. Table 43 shows the various FIR configuration options. Table 43. FIR Filter Configuration Options
Mode No FIR Filter 16QAM BPSK/QPSK BPSK/QPSK BPSK/QPSK Gain N/A Unity Unity x2 x3 Register 2E Bits 4-1 XXXX 1010 0000 1111 1010 Register 2C Bit 1 1 0 0 0 0
The interpolation filter contains accumulators. As the interpolation ratio grows larger, the number of accumulations per period of time increases. If the interpolation ratio becomes too large, the accumulator Table 44. FIR Filter Coefficient Storage
MSB (Bits 9-8) 0A H 0CH 0EH 10H E E 26H 28H 3BH 3DH E E 56H 58H 5A H Note: LSB (Bits 7-0) 09H 0BH 0DH 0F H E E 25H 27H 3A H 3CH E E 55H 57H 59H Filter Taps Taps 16 and 47 Taps 17 and 46 Taps 18 and 45 Taps 19 and 44 E E Taps 30 and 33 Taps 31 and 32 Taps 0 and 63 Taps 1 and 62 E E Taps 13 and 50 Taps 14 and 49 Taps 15 and 48
Each of the 32-tap, linear phase, FIR filters use 16Eten-bit, coefficients, which are completely programmable for any symmetrical (mirror image) polynomial. The FIR filter coefficients are stored in addresses 09H - 28 H, using two addresses for each 10-bit coefficient as shown in Table 50. The coefficients are stored as TwoOs Complement numbers in the range -512 to +511 (200H to 1FF H). The filter is always constrained to have symmetrical coefficients, resulting in a linear phase response. This allows each coefficient to be stored once for two taps, as shown in Table 44. Interpolating Filter The Interpolating Filter, shown in Figure 37, is a configurable, three-stage, interpolating filter. The filter increases the STEL-2176Os sampling rate (to permit the wide range of RF carrier frequencies possible) by interpolating between the FIR filter steps at the master clock frequency. This smoothes the digital representation of the signal which removes spurious signals from the spectrum
For MSB storage, only bits 1-0 are used.
I1/Q1
FIR
X2
COEFFICIENT M U 0X 1
1M U 0X
L O G I C
OUT
I0/Q0
FIR
CLRFIR BYPASS
2
WCP-52992.c-4/26/97
Figure 36. Nyquist FIR Filter
STEL-2176
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User Manual
Transmitter Description
Data Enable Bypass 16 Sample Clock 3-Stage Differentiator 16 G a i n 32 3-Stage Integrator 11 2
together according to the register settings shown in Table 47. This provides control over the characteristics of the resulting RF signal by allowing either or both of the two products to be inverted prior to the addition. Data Enable Output. The TXDATAENO output is a modified replica of the TXDATAENI input. TXDATAENO is asserted as a high 2 symbols after TXDATAENI goes high and it is asserted as a low 13 symbols after TXDATAENI goes low. In this way, a high on the TXDATAENO line indicates the active period of the DAC during transmission of the data burst. However, if the guard time between the current and next data burst is less than 13 symbols, then the TXDATAENO line will be held high through the next burst. Table 45. Interpolation Filter Bypass Control
Number of Interpolation Stages Selected 3 2 2 1 Interpolation Filter Bypass Register 2B Bits 5,4 0E0 0E1 1E0 1E1
Gain Control
4
Master Clock
WCP 52993.c-5/2/97
Figure 37. Interpolation Filter Block Diagram will overflow which will destroy the output spectral characteristics. To compensate for this, the interpolation filter has a gain function. This gain is normally set empirically. If the output spectrum is broad band noise or if it appears correct but has regular momentary OhitsO of broad band spectral noise, then the digital gain is too high. The interpolation filter gain is the first place to adjust gain because it does not directly affect the shape of the signal spectrum and it has a very wide adjustment range. Overall, gain can affected in the FIR filter function, the interpolation gain function, and by the number of interpolation stages (and therefore accumulators) used. Normally, three interpolation stages are used, but there is a bypass option for use when the interpolation is very high. It should be used only as a last resort after all other gain reduction options have been exercised because of the severe impact to spurious performance. The register bits that affect the interpolation filter functions are shown in Table 45 and Table 46. Modulator The interpolated I and Q data signals are input from the Interpolation Filter, fed into two complex modulators, and multiplied by the sine and cosine carriers which are generated by the NCO. The I channel signal is multiplied by the cosine output from the NCO and the Q channel signal is multiplied by the sine output. The resulting modulated sine and cosine carriers are applied to an adder and either added or subtracted
Table 46. Interpolation Filter Signal Level Control
Gain Factor (Relative) 20 21 2 2 2 2 2 2 2 2 2 2
2
Filter Gain Control Register 2A Bits 7-4 0H 1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH
23
4 5 6
27
8 9
10
2 11
12 13 14
2 15
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STEL-2176
Transmitter Description
Table 47. Signal Inversion Control
Output of Adder Block Sum = I . cos(t) + Q . sin(t) Sum = I . cos(t) + Q . sin(t) Sum = I . cos(t) Q . sin(t) Sum = I . cos(t) Q . sin(t) Invert I/Q Channel Register 2B Bits 1,0 0E0 0E1 1E0 1E1
10-Bit DAC The 10-bit Digital-to-Analog Converter (DAC) receives the modulated digital data and the Master clock. The DAC samples the digital data at the rate of the Master
clock and outputs a direct analog RF signal at a frequency of 5 to 65 MHz. The DAC outputs, DACOUTP and DACOUTN, are complementary current sources designed to drive double terminated 50 or 75 (25 or 37.5 total) load to ground. The nature of digitally sampled signals creates an image spur at a frequency equal to the Master Clock minus the output RF frequency. This image spur should be filtered by a user supplied low pass filter. For best overall spurious performance, the gain of the STEL2176 should be the highest possible (before digital overflow occurs - see Interpolation Filter discussion).
CONTROL UNIT DESCRIPTION
Bus Interface Unit The Bus Interface Unit (BIU) is part of the Microcontroller Interface (see page 11). If contains the Block 2 Registers (90 programmable 8-bit registers). The Reset ( TXRSTB) input signal is the master reset for the STEL-2176. Asserting a low on TXRSTB will reset the contents of all Block 2 Registers to 00 H (as well as clearing the data path registers). Asserting a high on TXRSTB enables normal operation. After power is applied and prior to configuring the STEL-2176, a low should be asserted on TXRSTB. Since TXRSTB is asynchronous, the TXCLKEN input should be held low whenever TXRSTB is low. The parallel address bus (ADDR 5-0) is used to select one of the 90 Block 2 Registers by placing its address on the ADDR5-0 bus lines. The data bus (DATA7-0) is an 8-bit, bi-directional data bus for writing data into or reading data from the selected Block 2 Register. The access operation is performed using the control signals DSB , CS , and WRB . The Chip Select ( CS ) input signal is used to enable or disable access operations to the STEL-2176. When a high is asserted on CS , all access operations are disabled and a low is asserted to enable the access operations. The CS input only affects Block 2 Register access and has no effect on the data path. The Data Strobe ( DSB ) input signal is used to write the data that is on the data bus (DATA7-0) into the Block 2 Register selected by ADDR 5-0 . The Write/Read ( WRB ) input signal is used to control the direction of the Block 2 Register access operation. When WRB is high, the data in the selected Block 2 Register is output onto the DATA7-0 bus. When WRB is low, the rising edge of DSB is used to latch the data on the DATA 7-0 bus into the selected Block 2 Register. (Refer to the Write and Read Timing diagrams in the Timing Diagrams section.) Some of the Block 2 Register data fields are used for factory test and must be set to specific values for normal operation. These values are noted in Table 50. Master Transmit Clock Generator The STEL-2176 uses a master clock (CLK) to control the transmit timing functions. CLK can be generated in either of three ways as shown in Figure 38. A transmit bypass clock can be applied to the TXBYPCLK input and selected to drive CLK. An external clock can be applied to the TXOSCIN input or a crystal can be connected across the TXOSCIN and TXOSCOUT inputs. The oscillator circuit outputs a 20-50 MHz signal to a frequency multiplier PLL, which upconverts the signal to a 100-150 MHz clock. When the bypass clock is not used, the multiplexer is set to select the output of the frequency multiplier to drive the CLK signal. The frequency multiplier output can also be routed to the TXPLLCLK output for test purposes.
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Transmitter Description
ENCLKOUT
TXPLLCLK OSCILLATOR FREQUENCY MULTIPLIER PLL MUX CLK (100-165 MHz)
TXOSCIN (20-50 MHz)
TXOSCOUT TXPLLEN TXBYPCLK TXBYPASSFSYN WCP 53854.c-12/8/97
Figure 38. Master Clock Generation Clock Generator The timing of the STEL-2176 is controlled by the Clock Generator, which uses an master clock (CLK) and programmable dividers to generate all of the internal and output clocks. There are primarily two clock systems, the auxiliary clock and the data path timing signals (bit, symbol, and sampling rate signals). The auxiliary clock (TXACLK) output is primarily for use in master mode where users may need a clock to run control circuits during the guard time between bursts (when TXCLKEN is low and TXBITCLK has stopped). The output clock rate is set by the frequency (f CLK) of the external master clock and the value (N) of the Auxiliary Clock Rate Control field (bits 3-0 of Block 2 Register 2AH). The clock rate is set to: TXACLK = Symbol Rate =
1 fCLK 4 N + 1 3 N 4095
The symbol pulse (TXSYMPLS) signal output is intended to allow the user to verify synchronization of the external serial data (TXTSDATA) with the STEL-2176 symbol timing. TXSYMPLS is normally low and pulses high for a period of one CLK cycle at the point where the last bit of the current symbol is internally latched by the falling edge of the internal BIT Clock (TXBITCLK) signal. (Refer to the Timing Diagrams section.) The internal TXBITCLK period is a function of the MOD field (bits 3-2 of Block 2 Register 2CH), which determines the signal modulation. TXBITCLK has a 50% duty cycle for BPSK and QPSK modes. It also has a 50% duty cycle in 16QAM mode when N+1 is even. If N+1 is odd, then TXBITCLK will be high for (N/2)+1 clocks and then low for N/2 clocks. (Refer to the Bit Clock Synchronization Timing diagram in the Timing Diagrams section.) The TXBITCLK frequency is determined by :
K = 1 for 16QAM, 2 for QPSK, 4 for BPSK 3 N 4095
fCLK N +1 2 N 15
If N is set to 1 or 0, the TXACLK output will remain set high, thereby disabling this function. If the TXACLK signal is not required, it is recommended that it be set in this mode to conserve power consumption. The TXACLK output is a pulse that will be high for 2 cycles of CLK and low for (N-1) CLK cycles. Unlike other functions, the TXACLK output is not affected by TXCLKEN. The data path timing is based on the ratio of the master clock frequency to the symbol data rate. The ratio must be a value of four times an integer number (N+1). The value of N must be in the range of 3 to 4095. This value is represented by a 12-bit binary number that is programmed by LSB and MSB Sampling Rate Control fields [Block 2 Register 29H (LSB) and bits 3-0 of Block 2 Register 39 H (MSB)], which sets the TXSYMPLS frequency [based on the frequency (f CLK) of the external master clock] to: User Manual
BITCLK =
CLK (N+1) K
NCO A 24-bit, Numerically Controlled Oscillator (NCO) is used to synthesize a digital carrier for output to the Modulator. The NCO gives a frequency resolution of about 6 Hz at a clock frequency of 100 MHz. The NCO also uses 12-bit sine and cosine lookup tables (LUTs) to synthesize a carrier with very high spectral purity, typically better than -75 dBc at the digital outputs.
53
STEL-2176
Transmitter Description
The STEL-2176 provides register space for three different carrier frequencies. The carrier frequency that will drive the modulator is selected by the TXFCWSEL10 control pin input signals. A high on the TXNCOLD input pin causes the registers selected by TXFCWSEL to drive the NCO at the frequency determined by the register value. The NCOOs frequency is programmable using the NCO field (Block 2 Registers 08 H -00H). The nine 8-bit registers at addresses 00H through 08H are used to store the three 24-bit frequency control words FCW OAO, FCW OBO and FCW OCO as shown in Table 48.
The output carrier frequency of the NCO (fCARR) will be:
fCARR =
fCLK . FCW 224
where, fCLK is the frequency of the CLK input signal. The FZSINB field (bit 7 Block 2 Register 2DH) controls the sine component output of the NCO. This can be used in BPSK to rotate the constellation 45 degrees (to Oon axisO modulation). For normal operation, it should be set to one.
Table 48. FCW Selection
TXFCWSEL1-0 00 01 10 11 FCW Selected FCW A FCW B FCW C Zero Frequency 23 - 16 Register 02H Bits 7 - 0 Register 05H Bits 7 - 0 Register 08H Bits 7 - 0 FCW Value Bits 15 - 8 Register 01H Bits 7 - 0 Register 04H Bits 7 - 0 Register 07H Bits 7 - 0 7-0 Register 00H Bits 7 - 0 Register 03H Bits 7 - 0 Register 06H Bits 7 - 0
TRANSMIT REGISTER DESCRIPTIONS
Programming the 2176 Transmit and Receive Functions The STEL-2176 has a total of xxx registers and they are arranged as three banks of registers. As indicated in Table 49, Bank 0 is sub-divided into two groups of registers which yields a total of four register groups. Table 49 shows the Bank Address that must be written to location FFH in order to access the respective register group. The registers comprising The Bank 0 and Bank 1 registers are described in the Receiver Section (see page 20). The registers comprising Bank 2 are described below. When the Bank 2 (Group 4) registers are accessed, the hexadecimal register addresses listed in Table 50 are sent to the Microcontroller Interface (see page 11) for doing a read or write operation on a specific register.
Table 49. Addresses of the STEL-2176 Register Groups
Group 1 2 3 4 Bank 0 0 1 2 Universal Registers QAM Demodulator Registers Universal Registers Downstream FEC Registers Upstream, or transmitter, Registers Group Name Bank Address (location FFH) 00H 00H 01H 02H
Block 2, Upstream Registers (Group 4) Description Each of the Block 2 registers (see Table 50) is an 8-bit, Read/Write register and each register contains one or more data fields, described below. The data fields are STEL-2176 the transmit parameters which control the transmit characteristics of the STEL-2176. When a transmit parameter requires more than 8 bits, it is stored in multiple data fields and stored used two or more registers.
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Transmitter Description
Table 50. Transmit Block 2 Register Data Fields
Address
08-00 28-09 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A-59
Bit7
Bit6
DCINB TCLK Sel. FZSIN MAPBPB
PP DATAENBP
Bit3 Bit2 Bit1 Bit0 NCO Frequency Control Word FIR Filter Coefficients Sampling Rate Control CIC Filter Gain Control Auxiliary Clock Rate Control ICIN Int. Filt. Bypass MSB ACCIN Invert I/Q Chan. ENDAC FWDB GAINB PN Sel PN Mod NITV LSB REV GAINB PN Sel PN Mod MAPSEL CLRFIR Sync TEST SCRAMBLER Init Reg [7:0] SCRAMBLER Init Reg [15:8] SCRAMBLER Init Reg[23:16] SCRAMBLER Mask Reg [7:0] SCRAMBLER Mask Reg[15:8] SCRAMBLER Mask Reg[23:16] BPB S-RS ssync T K DATARSENBP RSENSSCRMESCRMDiffDC-BP DiffDCS-EL ENSEL EL NBP ENSEL TRLSBP LDLSBF MSB Sampling rate FIR Filter Coefficients
Bit5
Bit4
Transmit Parameter Descriptions Auxiliary Clock Rate Divider Bit Mapping Bit Sync Re-arm BypassB CLRFIR DATAENBPB DATAENSEL DiffDCBPB DiffDCSEL ENDAC Sets the divide-by ratio of fCLK for generating an output clock for use with external control circuits. Selects the Bit-to-Symbol mapping option when QPSK or 16QAM modulation is selected. Used to arm the TXBITCLK synchronization circuit when TXCLKEN cannot be applied low between bursts. Allows the Scrambler and Reed-Solomon Encoder to be bypassed. Controls the Gain of the FIR Filter. Continuously enables or disables the input multiplexer of the Bit Encoder Block. Selects software (DATAENBPB) or hardware (input pin 109) control for enabling the input multiplexer of the Bit Encoder Block. Allows the Differential Encoder to be bypassed. Selects software (DiffDCBPB) or hardware (input pin 116) control for enabling the Differential Encoder. Setting this bit to 0 will make the DAC output enable controlled by the TXDATAENO signal (see page 65). Setting it to 1 will make the DAC enabled all the time. The default is 0. Controls routing of I/Q data through or around the FIR filters. Sixteen 10-bit FIR coefficients. Each coefficient is applied to two taps of the FIR filter to control its filter characteristics. Controls the sine component of the NCO output. Setting the field to 0 rotates the constellation by 45 for on-axis modulation of a BPSK signal.
FIR bypass FIR Filter Coefficients FZSINB
User Manual
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STEL-2176
Transmitter Description
Interpolation Filt. Bypass Interpolation Filter Gain Control Invert I/Q Chan. K LDLSBF LSB Sampling Rate Control MOD NCO PN Code Sel PN On/Off PPolynomial RSENBPB RSENSEL SCRAMBLER Init Registers SCRAMBLER Mask Registers SCRMENBPB SCRMENSEL Self-Sync S-RS Symbol Mapping T TCLK Sel. TRLSBF
Controls the number of filter stages the Interpolation Filter will use for filtering the signal. Sets the gain of the Interpolation Filter. Controls the signal inversion of the I and Q channels by using an adder to add or subtract the two channels. Defines the length of the User Data Packet in bytes. Determines whether the MSB or LSB of the checksum byte is to be output as the first bit of the serial output data. A 12-bit word that controls the sampling rate of the 10-Bit DAC. Register 29 contains the 8 LSBs and Register 39 contains the 4 MSBs. Selects type of modulation (BPSK, QPSK, or 16QAM). Three 24-bit frequency control words. The word selected for setting the frequency of the NCO carrier is selected by the input pins TXFCWSEL[1-0] . Selects one of two PN codes when pseudo-random generator is enabled. Enables or disables the pseudo-random generator Selects one of two primitive polynomials for use with the Reed-Solomon Encoder for encoding data. Allows the Reed-Solomon Encoder to be bypassed. Selects software (RSENBPB) or hardware (input pin 117) control for enabling the ReedSolomon Encoder. A 24-bit word that is loaded into the PN generator to initialize its shift register. A 24-bit word that is masks the output of the PN generator shift register. Allows the Scrambler to be bypassed. Selects software (SCRMENBPB) or hardware (input pin 118) control for enabling the Scrambler. Controls selection of the self sync or frame sync signal for routing back to the PN generator shift circuit. Controls whether the input data is to be scrambled then encoded by the Scrambler and Reed-Solomon Encoder or whether it is to be encoded then scrambled. Selects one of five symbol mapping options when 16QAM modulation is selected. Sets the error correction capability of the error correction encoding. Selects an externally generated clock for external control of data latching. Determines whether the first input bit is the MSB or LSB of the byte applied to the RS Encoder.
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User Manual
Transmitter Description
TIMING DIAGRAMS
CLOCK TIMING
tCLK
CLK tCLKH tr tf
WCP 52787.c-12/5/97
tCLKL
Table 51. Clock Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol Parameter Clock Frequency ( tCLK tCLKH tCLKL tR tF Clock Period Clock High Period Clock Low Period Clock Rising Time Clock Falling Time
1 t CLK
Min.
Nom.
) 6 2.5 2.5
Max. 165
Units MHz nsec nsec nsec
Conditions
0.5 0.5
nsec nsec
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STEL-2176
Transmitter Description
TRANSMIT PULSE WIDTH
tCEL
TXCLKEN
tRSTL
TXRSTB
TXNCOLD
tNLDH
WCP 53811.c-12/5/97
Table 52. Pulse Width AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tCEL tRSTL tNLDH Parameter Clock Enable (TXCLKEN) Low Reset (TXRSTB) Low NCO Load (TXNCOLD) High Min. 4 5 1 Nom. Max. Units nsec nsec CLK cycles Conditions
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Transmitter Description
BIT CLOCK SYNCHRONIZATION
TXACLK TXCLKEN TXTCLK
tCO tCO
tCESU
TXBITCLK
2 (N +1) BPSK (N +1) QPSK See Note 1 N +1 16QAM 2 n = Odd N +2 16QAM 2 n = Even
WCP 53826.c-12/5/97
See Note 2
Note 1: TXBITCLK will be forced high on the second rising edge of CLK following the rising edge of TXTCLK. Note 2: The period of time that TXBITCLK is high is measured in cycles of CLK (e.g. (N + 1) in QPSK). "N" is a 12-bit binary number formed by taking bits 3-0 of Block 2 Register 39H as the MSB's and taking bits 7-0 of Block 2 Register 29 H as the LSB's. The TXBITCLK low period is the same except for 16QAM when "N" is even in which case the low period is (N/2) yielding the correct TXBITCLK period but not a perfect squarewave. Table 53. Bit Clock Synchronization AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tCO tCESU TXACLK edge Clock Enable (TXCLKEN to TXTCLK Setup) 3 nsec Parameter Clock to TXBITCLK, TXSYMPLS, TXDATAENO, or Min. Nom. Max. 2 Units nsec Conditions
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STEL-2176
Transmitter Description
TRANSMIT INPUT DATA AND CLOCK TIMING SLAVE MODE MASTER MODE
TXAUXCLK TXTCLK TXTCLK DON'T CARE
NOTE 1
NOTE 1
TXBITCLK NOTE 2 DON'T CARE tSU TXTSDATA tHD
TXBITCLK
NOTE 3
tCLK tSU tHD
TXTSDATA
Note 1: Mode is determined by setting of BIT 7 in Block 2 Register 2C H. Bit 7 high is slave mode; Bit 7 low is master mode. Note 2: In slave mode, even though TXBITCLK is shown as ODon't CareO, it should be noted that internally the STELE2176 will relatch the data on the next falling edge of TXBITCLK. Thus, avoid changing the control signal inputs (TXDATAENI, TXDIFFEN, TXRDSLEN, TXSCRMEN) at the falling edges of TXBITCLK. Note 3: In the STEL-2176, data is latched on the rising edge of the CLK that follows the falling edge of TXBITCLK. Thus, the data validity window is one CLK period (tCLK) delayed. CLK not shown. Table 54. Input Data and Clock AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tCLK tSU tHD Clock Period TXTSDATA to Clock Setup TXTSDATA to Clock Hold Parameter Min. 6 2 2 Nom. Max. Units nsec nsec nsec Conditions
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User Manual
Transmitter Description
WRITE TIMING
tAVA tWAHD tWASU
Address ADDR[5-0]
tCSHD tCSSU
CS
tWRSU tWRHD
WRB
tDSBL
DSB
tDH tDSU
Data DATA[7-0]
WCP 53814.c-12/5/97
Table 55. Write Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tWASU tWAHD tAVA tCSSU tCSHD tWRSU tWRHD tDSBL tDH tDSU Parameter Write Address Setup Write Address Hold Address Valid Period Chip Select ( CS ) Setup Chip Select ( CS ) Hold Write Setup ( WRB ) Write Hold ( WRB ) Data Strobe Pulse Width Data Hold Time Data Setup Time Min. 10 6 20 5 3 5 3 10 1 3 Nom. Max. Units nsec nsec nsec nsec nsec nsec nsec nsec nsec nsec Conditions
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STEL-2176
Transmitter Description
READ TIMING
tAVA tADV
Address7-0 CS
WRB
tDICSH tDVCSL tADIV
Data7-0
WCP 53815.c-12/2/97
Table 56. Read Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tAVA tADV tADIV tDVCSL tDICSH Parameter Address Valid Period Address to Data Valid Delay Address to Data Invalid Delay Data Valid After Chip Select Low Data Invalid After Chip Select High 6 2 1 Min. 20 9 Nom. Max. Units nsec nsec nsec nsec nsec Conditions
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Transmitter Description
NCO LOADING (USER CONTROLLED)
OUTPUT
tFCWHD tFCWSU OLD FREQ. NEW FREQ.
TXFCWSEL1-0 DON'T CARE TXNCOLD
NOTE 1
VALID
DON'T CARE tLDPIPE
WCP 53816.c-12/5/97
NCO LOADING (AUTOMATIC)
OUTPUT
ZERO tDENHV
SELECTED FREQUENCY
ZERO
TXFCWSEL1-0 DON'T CARE TXDATAENO
tDOFCWV
VALID
DON'T CARE tDENLZ
tDOFCWI
WCP 53817.c-12/5/97
NOTE 1: The first rising edge of CLK after TXNCOLD goes high initiates the load process. Table 57. NCO Loading AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tLDPIPE tFCWSU tFCWHD tDENLZ tDENHV tDOFCWV tDOFCWI Delay TXFCWSEL 1-0 to NCO-LD Setup TXFCWSEL 1-0 to NCO-LD Hold TXDATAENO Low to Zero Frequency Out Delay TXDATAENO High to Valid Frequency Out Delay TXDATAENO to TXFCWSEL1-0 Valid TXDATAENO to TXFCWSEL1-0 Invalid 10 3 CLK cycles CLK cycles 10 23 23 3 CLK cycles CLK cycles CLK cycles CLK cycles Parameter NCO-LD to Change in Output Frequency Pipeline Min. Nom. 23 Max. Units CLK cycles Conditions
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STEL-2176
Transmitter Description
DIGITAL OUTPUT TIMING
CLK
tCO tCO tACKH tACKL
TXACLK Note 1
TXBITCLK
tCO tSPH
TXSYMPLS
tCO
TXDATAENO
tCO tDENOD
WCP 53818.c-12/7/97
NOTE 1:
TXACLK shown for "n" equal to 2: where n is the 4-bit binary value in Block 2 Register 2AH, BITSE3-0. Table 58. Digital Output Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tCO tACKH tACKL tSPH tDENOD Notes: 1. or TXACLK edge
Parameter Clock to TXBITCLK, TXSYMPLS, TXDATAENO, Auxiliary Clock (TXACLK) High Auxiliary Clock (TXACLK) Low Symbol Pulse (TXSYMPLS) High TXBITCLK Low to TXDATAENO edge
Min.
Nom.
Max. 2
Units nsec CLK cycles CLK cycles CLK cycles CLK cycles
Conditions
2 (n-1) 1 1
Note 1
OnO is the 4-bit binary value in Block 2 Register 2AH , bits 3-0.
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Transmitter Description
TXDATAENI TO TXDATAENO TIMING
tDENSP
TXDATAENI
tDIHDO tSPDEN tSPDEN tDLDO tDENSP
TXDATAENO
TXSYMPLS
WCP 53819.c-12/5/97
Table 59. TXDATAENI to TXDATAENO Timing AC Characteristics (V DD = 3.3 V 10%, VSS = 0 V, Ta = 40 to 85 C)
Symbol tDIHDO tDLDO tSPDEN tDENSP Notes: 1. Shown for Block 2 Register 36H, bit 6=0 (No Reed-Solomon). If bit 6 of Register 36H is a O1O, then the edges of TXDATAENO will be delayed from those illustrated by 8, 4, or 2 TXSYMPLS for BPSK, QPSK, or 16QAM, respectively. Parameter TXDATAENI High to TXDATAENO High TXDATAENI Low to TXDATAENO Low TXSYMPLS (trailing edge) to TXDATAENI Setup TXDATAENI to TXSYMPLS (trailing edge) Setup 3 5 Min. Nom. 2
nd th
Max.
Units TXSYMPLS TXSYMPLS nsec nsec
Conditions Note 1 Note 1
13
BURST TIMING EXAMPLES
The following seven timing diagrams are qualitative in nature and meant to illustrate the functional relationships between the control inputs and signal outputs in various modes of burst operation. Use the key at right to interpret the timing marks. Only the first diagram is of a complete and realistic burst. The remaining diagrams are too short in duration to show TXDATAENO and TXCLKEN going low.
Key:
WAVEFORM INPUTS Must be Steady May Change from H to L May Change from L to H Don't Care. Any Change Permitted Does Not Apply OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing. State Unknown Center Line is HighImpedance "Off" State
WCP 53036.c-5/6/97
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STEL-2176
Introduction
SLAVE MODE, QPSK - BURST TIMING: FULL BURST
NAME TXTCLK(1) TXTSDATA TXCLKEN TXDATAENI TXDATAENO(2) TXDIFFEN(3) TXRDSLEN TXSCRMEN (A) (B) (C) (D) (E) (L) (L) (H) (M) (N) (I) (K) (F) (G) (J)
Preamble TXSYMPLS
User Data
Guard Time
WCP 53820.c -12/5/97
NOTES: (1) All input signals shown are derived from TXTCLK. Each edge is delayed from a TXTCLK edge by typically 6 to 18 nsec. DATAENO does not depend on TXTCLK but its edges are synchronized to TXTCLK. TXTCLK itself can be turned off after TXDATAENI goes low. DATAENO shown at its minimum pipeline delay position. This is achieved by setting bit 6 of Block 2 Register 36 H to zero. Reed-Solomon cannot be used in this mode. If bit 6 is set high, allowing Reed-Solomon an additional pipeline delay of 8Ebits is inserted into the data path. This will shift both edges of DATAENO to the right by 8 cycles of TXTCLK. If the preamble is not encoded the same as the user data, the TXDIFFEN control can be toggled in mid transmission as shown. Otherwise, the TXDIFFEN control can be held high or low depending on encoding desired.
(2)
(3)
(A) First data bit transition on falling edge of TXTCLK (first of 14 preamble symbols). The data will be valid on the next rising edge of TXTCLK. (B) TXCLKEN rises on the same falling edge of TXTCLK that the data starts on. TXCLKEN is allowed to rise any time earlier than shown. (C) TXDATAENI rises on the first rising edge of TXTCLK (middle of the first preamble bit). (D) DATAENO rises on the falling edge of TXTCLK (at the end of the second symbol). (E) TXDIFFEN rises on the rising edge of TXTCLK one symbol before the first user data symbol. (F) User data bits change on the falling edge of TXTCLK and must be valid during the next rising edge of TXTCLK. (G) End of user data. Note that the data is allowed to go away immediately after it is latched in by the rising of TXTCLK which occurs in the middle of the last user data bit. (H) TXDIFFEN goes low on rising edge of TXTCLK (last user data symbol). (I) (J) TXDATAENI goes low on rising edge of TXTCLK (on the cycle of TXTCLK after the last user data bit). TXCLKEN must stay high until any time on or after the point where DATAENO goes low.
(K) DATAENO stays high until the 13th TXSYMPLS after TXDATAENI goes low. (L) TXRDSLEN and TXSCRMEN go high on the first rising edge of TXTCLK in the User Data. (M) TXRDSLEN goes low on the rising edge of TXTCLK (last user data symbol). (N) TXSCRMEN goes low on the rising edge of TXTCLK (on the cycle of TXTCLK after the last user data bit).
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MASTER MODE, BPSK - BURST TIMING SIGNAL RELATIONSHIPS
TXCLKEN TXBITCLK TXTCLK TXDATAEN TXTSDATA
GUARD TIME
PI
PI
PI
PI
UI
NOTE 1
UI
UI
UI
GI
GI
GI
GI
PREAMBLE
USER DATA
GUARD TIME
TXDIFFEN TXRDSLEN TXSCRMEN TXSYMPLS TXDATAENO
NOTE 2
WCP 53837.c-12/5/97
SLAVE MODE, BPSK - BURST TIMING SIGNAL RELATIONSHIPS
TXCLKEN TXBITCLK TXTCLK TXDATAEN TXTSDATA TXDIFFEN TXRDSLEN TXSCRMEN TXSYMPLS TXDATAENO
NOTE 2 GUARD TIME
PI
PI
PI
PI
UI
UI
NOTE 1
UI
UI
GI
GI
GI
GI
PREAMBLE
USER DATA
GUARD TIME
WCP 53838.c-12/5/97
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring TXDIFFEN high at the leading edge of the user data packet (dotted line). If bit 6 of Block 2 Register 36H is a "1" then the rising edge of DATAENO will be delayed by eight cycles of TXBITCLK (dotted line). This is required if the ReedSolomon encoder is used.
NOTE 2:
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Transmitter Description
MASTER MODE, QPSK - BURST TIMING SIGNAL RELATIONSHIPS
TXCLKEN TXBITCLK TXTCLK TXDATAEN TXTSDATA GUARD TIME TXDIFFEN TXRDSLEN TXSCRMEN TXSYMPLS TXDATAENO NOTE 2
WCP 53821.c-12/5/97
PI
PQ
PI
PQ
UI
UQ
UI
UQ
GI
GQ
GI
GQ
PREAMBLE NOTE 1
USER DATA
GUARD TIME
SLAVE MODE, QPSK: FULL VIEW - BURST TIMING SIGNAL RELATIONSHIPS
TXCLKEN TXBITCLK TXTCLK TXDATAENI TXTSDATA GUARD TIME TXDIFFEN TXRDSLEN TXSCRMEN TXSYMPLS TXDATAENO NOTE 2
WCP 53822.c-12/5/97
PI
PQ PI PREAMBLE
PQ
UI
UQ UI USER DATA
UQ
GI
GQ GI GUARD TIME
GQ
NOTE 1
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring TXDIFFEN high at the leading edge of the user data packet (dotted line). If bit 6 of Block 2 Register 36H is a "1" then the rising edge of DATAENO will be delayed by eight cycles of TXBITCLK (dotted line). This is required if the ReedSolomon encoder is used.
NOTE 2:
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MASTER MODE, 16QAM - BURST TIMING SIGNAL RELATIONSHIPS
TXCLKEN TXBITCLK TXTCLK TXDATAENI TXTSDATA
GUARD TIME
PI1 PQ1 PI0 PQ0 PI1 PQ1 PI0 PQ0 UI1 UQ1 UI0 UQ0 UI1 UQ1 UI0 UQ0 GI1 GQ1 GI0 GQ0 GI1 GQ1 GI0 GQ0
PREAMBLE NOTE 1
USER DATA
GUARD TIME
TXDIFFEN TXRDSLEN TXSCRMEN TXSYMPLS TXDATAENO
NOTE 2
WCP 53823.c-12/5/97
NOTE 1:
STEL receivers differentially decode relative to the last preamble symbol. To encode the first symbol against a "zero" symbol reference instead, bring TXDIFFEN high at the leading edge of the user data packet (dotted line). If bit 6 of Block 2 Register 36H is a "1" then the rising edge of DATAENO will be delayed by eight cycles of TXBITCLK (dotted line). This is required if the ReedSolomon encoder is used.
NOTE 2:
SLAVE MODE, 16QAM - BURST TIMING SIGNAL RELATIONSHIPS
TXCLKEN TXBITCLK TXTCLK TXDATAENI TXTSDATA
GUARD TIME
PI1 PQ1 PI0 PQ0 PI1 PQ1 PI0 PQ0 UI1 UQ1 UI0 UQ0 UI1 UQ1 UI0 UQ0 GI1 GQ1 GI0 GQ0 GI1 GQ1 GI0 GQ0
PREAMBLE NOTE 1
USER DATA
GUARD TIME
TXDIFFEN TXRDSLEN TXSCRMEN TXSYMPLS TXDATAENO
NOTE 2
WCP 53824.c-12/5/97
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Transmitter Description
RECOMMENDED INTERFACE CIRCUITS
SLAVE MODE INTERFACE
TSDATA CLKEN
D
Q
TXTSDATA
D
Q
OR
TXCLKEN TXDATAENO
DATAEN
D
Q
TXDATAEN
STEL-2176
DIFFEN
D
Q 2
TXDIFFEN TXFCWSEL1-0 TXTCLK
WCP 52995.c-5/2/97
FCWSEL 1-0 TCLK
D
Q
MASTER MODE INTERFACE
TSDATA
D
Q
D
Q
TXTSDATA
BITCLK
DATAENI
D
Q
D
Q
TXDATAENI STEL-2176
DIFFEN
D
Q
D
Q
TXDIFFEN
D
Q
TXTCLK TXCLKEN*
WCP 52115A.c 5/2/97
*
TXCLKEN may be turned off between bursts to conserve power as long as it is kept on until after TXDATAENO goes low. Note that the TXBITCLK output goes inactive whenever TXCLKEN is low.
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Information in this document is provided in connection with Intel(R) products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intels Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied Intel may make changes to specifications and product descriptions at any time, without notice.
warranty, relating to sale and/or use of Intel(R) products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.
For Further Information Call or Write
INTEL CORPORATION Cable Network Operation 350 E. Plumeria Drive, San Jose, CA 95134 Customer Service Telephone: (408) 545-9700 Technical Support Telephone: (408) 545-9799 FAX: (408) 545-9888 WCP 970317
Copyright (c) Intel Corporation, December 15, 1999. All rights reserved

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